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io6Library
WIZnet Dual Stack TCP/IP Ethernet Controller Driver
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io6Library
WIZnet Dual Stack TCP/IP Ethernet Controller Driver
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W6100 HAL Header File. More...
Go to the source code of this file.
Macros | |
| #define | _W6100_SPI_READ_ (0x00 << 2) |
| SPI interface Read operation in Control Phase. More... | |
| #define | _W6100_SPI_WRITE_ (0x01 << 2) |
| SPI interface Write operation in Control Phase. More... | |
| #define | WIZCHIP_CREG_BLOCK (0x00 <<3) |
| Common register block. More... | |
| #define | WIZCHIP_SREG_BLOCK(N) ((1+4*N)<<3) |
| SOCKETn register block. More... | |
| #define | WIZCHIP_TXBUF_BLOCK(N) ((2+4*N)<<3) |
| SOCKETn Tx buffer address block. More... | |
| #define | WIZCHIP_RXBUF_BLOCK(N) ((3+4*N)<<3) |
| SOCKETn Rx buffer address block. More... | |
| #define | WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8)) |
| Increase offset address. More... | |
| #define | IDM_AR0 ((_WIZCHIP_IO_BASE_ + 0x0000)) |
| Indirect High Address Register. More... | |
| #define | IDM_AR1 ((_WIZCHIP_IO_BASE_ + 0x0001)) |
| Indirect Low Address Register. More... | |
| #define | IDM_BSR ((_WIZCHIP_IO_BASE_ + 0x0002)) |
| Block Select Register. More... | |
| #define | IDM_DR ((_WIZCHIP_IO_BASE_ + 0x0003)) |
| Indirect Data Register. More... | |
| #define | _W6100_IO_BASE_ _WIZCHIP_IO_BASE_ |
| #define | _CIDR_ (_W6100_IO_BASE_ + (0x0000 << 8) + WIZCHIP_CREG_BLOCK) |
| Chip Identification Register address [RO] [0x6100]. More... | |
| #define | _VER_ (_W6100_IO_BASE_ + (0x0002 << 8) + WIZCHIP_CREG_BLOCK) |
| Chip Version Register address [RO] [0x4661]. More... | |
| #define | _SYSR_ (_W6100_IO_BASE_ + (0x2000 << 8) + WIZCHIP_CREG_BLOCK) |
| System Status Register address [RO] [0xEU]. More... | |
| #define | _SYCR0_ (_W6100_IO_BASE_ + (0x2004 << 8) + WIZCHIP_CREG_BLOCK) |
| System Config Register 0 address [WO][0x80]. More... | |
| #define | _SYCR1_ (WIZCHIP_OFFSET_INC(_SYCR0_,1)) |
| System Config Register 1 address [R=W][0x80]. More... | |
| #define | _TCNTR_ (_W6100_IO_BASE_ + (0x2016 << 8) + WIZCHIP_CREG_BLOCK) |
| Ticker Counter Register address [RO][0x0000]. More... | |
| #define | _TCNTRCLR_ (_W6100_IO_BASE_ + (0x2020 << 8) + WIZCHIP_CREG_BLOCK) |
| Ticker Counter Clear Register address [RO][0x00]. More... | |
| #define | _IR_ (_W6100_IO_BASE_ + (0x2100 << 8) + WIZCHIP_CREG_BLOCK) |
| Interrupt Register address [RO][0x00]. More... | |
| #define | _SIR_ (_W6100_IO_BASE_ + (0x2101 << 8) + WIZCHIP_CREG_BLOCK) |
| SOCKET Interrupt Register address [RO][0x00]. More... | |
| #define | _SLIR_ (_W6100_IO_BASE_ + (0x2102 << 8) + WIZCHIP_CREG_BLOCK) |
| SOCKET-less Interrupt Register address [RO][0x00]. More... | |
| #define | _IMR_ (_W6100_IO_BASE_ + (0x2104 << 8) + WIZCHIP_CREG_BLOCK) |
| Interrupt Mask Register address [R=W][0x00]. More... | |
| #define | _IRCLR_ (_W6100_IO_BASE_ + (0x2108 << 8) + WIZCHIP_CREG_BLOCK) |
| _IR_ Clear Register address [WO][0x00] More... | |
| #define | _SIMR_ (_W6100_IO_BASE_ + (0x2114 << 8) + WIZCHIP_CREG_BLOCK) |
| SOCKET Interrupt Mask Register address [R=W]][0x00]. More... | |
| #define | _SLIMR_ (_W6100_IO_BASE_ + (0x2124 << 8) + WIZCHIP_CREG_BLOCK) |
| SOCKET-less Interrupt Mask Register address [R=W][0x00]. More... | |
| #define | _SLIRCLR_ (_W6100_IO_BASE_ + (0x2128 << 8) + WIZCHIP_CREG_BLOCK) |
| SOCKET-less Interrupt Clear Register address [WO][0x00]. More... | |
| #define | _SLPSR_ (_W6100_IO_BASE_ + (0x212C << 8) + WIZCHIP_CREG_BLOCK) |
| SOCKET-less Prefer Source IPv6 Address Register address [R=W][0x00]. More... | |
| #define | _SLCR_ (_W6100_IO_BASE_ + (0x2130 << 8) + WIZCHIP_CREG_BLOCK) |
| SOCKET-less Command Register address [RW,AC][0x00]. More... | |
| #define | _PHYSR_ (_W6100_IO_BASE_ + (0x3000 << 8) + WIZCHIP_CREG_BLOCK) |
| PHY Status Register address [RO][0x00]. More... | |
| #define | _PHYRAR_ (_W6100_IO_BASE_ + (0x3008 << 8) + WIZCHIP_CREG_BLOCK) |
| PHY Internal Register Address Register address(R/W) More... | |
| #define | _PHYDIR_ (_W6100_IO_BASE_ + (0x300C << 8) + WIZCHIP_CREG_BLOCK) |
| PHY Data Input Register address [R=W][0x00]. More... | |
| #define | _PHYDOR_ (_W6100_IO_BASE_ + (0x3010 << 8) + WIZCHIP_CREG_BLOCK) |
| PHY Data Output Register address [WO][0x00]. More... | |
| #define | _PHYACR_ (_W6100_IO_BASE_ + (0x3014 << 8) + WIZCHIP_CREG_BLOCK) |
| PHY Access Register address [RW,AC][0x00]. More... | |
| #define | _PHYDIVR_ (_W6100_IO_BASE_ + (0x3018 << 8) + WIZCHIP_CREG_BLOCK) |
| PHY's MDC Clock Division Register address [R=W][0x01]. More... | |
| #define | _PHYCR0_ (_W6100_IO_BASE_ + (0x301C << 8) + WIZCHIP_CREG_BLOCK) |
| PHY Control Register address [WO][0x00]. More... | |
| #define | _PHYCR1_ WIZCHIP_OFFSET_INC(_PHYCR0_,1) |
| PHY Control Register address [R=W][0x40]. More... | |
| #define | _NET4MR_ (_W6100_IO_BASE_ + (0x4000 << 8) + WIZCHIP_CREG_BLOCK) |
| Network IPv4 Mode Register address [R=W][0x00]. More... | |
| #define | _NET6MR_ (_W6100_IO_BASE_ + (0x4004 << 8) + WIZCHIP_CREG_BLOCK) |
| Network IPv6 Mode Register address [R=W][0x00]. More... | |
| #define | _NETMR_ (_W6100_IO_BASE_ + (0x4008 << 8) + WIZCHIP_CREG_BLOCK) |
| Network Mode Register address [R=W][0x00]. More... | |
| #define | _NETMR2_ (_W6100_IO_BASE_ + (0x4009 << 8) + WIZCHIP_CREG_BLOCK) |
| Network Mode Register 2 address [R=W][0x00]. More... | |
| #define | _PTMR_ (_W6100_IO_BASE_ + (0x4100 << 8) + WIZCHIP_CREG_BLOCK) |
| PPP LCP request Timer Register address [R=W][0x28]. More... | |
| #define | _PMNR_ (_W6100_IO_BASE_ + (0x4104 << 8) + WIZCHIP_CREG_BLOCK) |
| PPP LCP Magic Number Register address [R=W][0x00]. More... | |
| #define | _PHAR_ (_W6100_IO_BASE_ + (0x4108 << 8) + WIZCHIP_CREG_BLOCK) |
| PPPoE Hardware Address Register address [R=W][0x00]. More... | |
| #define | _PSIDR_ (_W6100_IO_BASE_ + (0x4110 << 8) + WIZCHIP_CREG_BLOCK) |
| PPP Session ID Register address [R=W][0X0000]. More... | |
| #define | _PMRUR_ (_W6100_IO_BASE_ + (0x4114 << 8) + WIZCHIP_CREG_BLOCK) |
| PPP Maximum Receive Unit Register address [R=W][0xFFFF]. More... | |
| #define | _SHAR_ (_W6100_IO_BASE_ + (0x4120 << 8) + WIZCHIP_CREG_BLOCK) |
| Source Hardware Address Register address [R=W][00:00:00:00:00:00]. More... | |
| #define | _GAR_ (_W6100_IO_BASE_ + (0x4130 << 8) + WIZCHIP_CREG_BLOCK) |
| IPv4 Gateway Address Register address [R=W][0.0.0.0]. More... | |
| #define | _GA4R_ (_GAR_) |
| Refer to _GAR_. More... | |
| #define | _SUBR_ (_W6100_IO_BASE_ + (0x4134 << 8) + WIZCHIP_CREG_BLOCK) |
| IPv4 Subnet Mask Register address [R=W][0.0.0.0]. More... | |
| #define | _SUB4R_ (_SUBR_) |
| Refer to _SUBR_. More... | |
| #define | _SIPR_ (_W6100_IO_BASE_ + (0x4138 << 8) + WIZCHIP_CREG_BLOCK) |
| IPv4 Source IP Register address [R=W][0.0.0.0]. More... | |
| #define | _SIP4R_ (_SIPR_) |
| Refer to _SIPR_. More... | |
| #define | _LLAR_ (_W6100_IO_BASE_ + (0x4140 << 8) + WIZCHIP_CREG_BLOCK) |
| IPv6 LLA(Link Local Address) Register address [R=W][::]. More... | |
| #define | _GUAR_ (_W6100_IO_BASE_ + (0x4150 << 8) + WIZCHIP_CREG_BLOCK) |
| IPv6 GUA(Global Unicast Address) Register address [R=W][::]. More... | |
| #define | _SUB6R_ (_W6100_IO_BASE_ + (0x4160 << 8) + WIZCHIP_CREG_BLOCK) |
| IPv6 Subnet Mask Register address [R=W][]. More... | |
| #define | _GA6R_ (_W6100_IO_BASE_ + (0x4170 << 8) + WIZCHIP_CREG_BLOCK) |
| IPv6 Gateway Address Register address [R/W][::]. More... | |
| #define | _SLDIP6R_ (_W6100_IO_BASE_ + (0x4180 << 8) + WIZCHIP_CREG_BLOCK) |
| SOCKET-less Peer IPv6 Register address [R=W][::]. More... | |
| #define | _SLDIPR_ (_W6100_IO_BASE_ + (0x418C << 8) + WIZCHIP_CREG_BLOCK) |
| SOCKET-less Peer IPv6 Register address [R=W][0.0.0.0]. More... | |
| #define | _SLDIP4R_ (_SLDIPR_) |
| Refer to _SLDIPR_. More... | |
| #define | _SLDHAR_ (_W6100_IO_BASE_ + (0x4190 << 8) + WIZCHIP_CREG_BLOCK) |
| SOCKET-less Peer Hardware Address Register address [RO][00:00:00:00:00:00]. More... | |
| #define | _PINGIDR_ (_W6100_IO_BASE_ + (0x4198 << 8) + WIZCHIP_CREG_BLOCK) |
| SOCKET-less Ping ID Register address [R=W][0x00]. More... | |
| #define | _PINGSEQR_ (_W6100_IO_BASE_ + (0x419C << 8) + WIZCHIP_CREG_BLOCK) |
| SOCKET-less ping Sequence number Register address [R=W][0x0000]. More... | |
| #define | _UIPR_ (_W6100_IO_BASE_ + (0x41A0 << 8) + WIZCHIP_CREG_BLOCK) |
| IPv4 Unreachable Address Register address [RO][0.0.0.0]. More... | |
| #define | _UIP4R_ (_UIPR_) |
| Refer to _UPORTR_. More... | |
| #define | _UPORTR_ (_W6100_IO_BASE_ + (0x41A4 << 8) + WIZCHIP_CREG_BLOCK) |
| IPv4 Unreachable Port number Register address [RO][0x0000]. More... | |
| #define | _UPORT4R_ (_UPORTR_) |
| Refer to _UPORTR_. More... | |
| #define | _UIP6R_ (_W6100_IO_BASE_ + (0x41B0 << 8) + WIZCHIP_CREG_BLOCK) |
| IPv6 Unreachable IP Address Register address [RO][::]. More... | |
| #define | _UPORT6R_ (_W6100_IO_BASE_ + (0x41C0 << 8) + WIZCHIP_CREG_BLOCK) |
| IPv6 Unreachable Port number Register address [RO][0x0000]. More... | |
| #define | _INTPTMR_ (_W6100_IO_BASE_ + (0x41C5 << 8) + WIZCHIP_CREG_BLOCK) |
| Interrupt Pending Time Register address [R=w][0x0000]. More... | |
| #define | _PLR_ (_W6100_IO_BASE_ + (0x41D0 << 8) + WIZCHIP_CREG_BLOCK) |
| RA Prefix Length Register address [RO][0x00]. More... | |
| #define | _PFR_ (_W6100_IO_BASE_ + (0x41D4 << 8) + WIZCHIP_CREG_BLOCK) |
| RA Prefix Flag Register address [RO][0x00]. More... | |
| #define | _VLTR_ (_W6100_IO_BASE_ + (0x41D8 << 8) + WIZCHIP_CREG_BLOCK) |
| RA Valid Life Time Register address [RO][0x00000000]. More... | |
| #define | _PLTR_ (_W6100_IO_BASE_ + (0x41DC << 8) + WIZCHIP_CREG_BLOCK) |
| RA Prefered Life Time Register address [RO][0x00000000]. More... | |
| #define | _PAR_ (_W6100_IO_BASE_ + (0x41E0 << 8) + WIZCHIP_CREG_BLOCK) |
| RA Prefix Address Register address[RO][::]. More... | |
| #define | _ICMP6BLKR_ (_W6100_IO_BASE_ + (0x41F0 << 8) + WIZCHIP_CREG_BLOCK) |
| ICMPv6 Block Register address [R=W][0x00]. More... | |
| #define | _CHPLCKR_ (_W6100_IO_BASE_ + (0x41F4 << 8) + WIZCHIP_CREG_BLOCK) |
| Chip configuration Lock Register address [WO][0x00]. More... | |
| #define | _NETLCKR_ (_W6100_IO_BASE_ + (0x41F5 << 8) + WIZCHIP_CREG_BLOCK) |
| Network configuration Lock Register address [WO][0x00]. More... | |
| #define | _PHYLCKR_ (_W6100_IO_BASE_ + (0x41F6 << 8) + WIZCHIP_CREG_BLOCK) |
| PHY configuration Lock Register address [WO][0x00]. More... | |
| #define | _RTR_ (_W6100_IO_BASE_ + (0x4200 << 8) + WIZCHIP_CREG_BLOCK) |
| Retransmission Time Register address [R=W][0x07D0]. More... | |
| #define | _RCR_ (_W6100_IO_BASE_ + (0x4204 << 8) + WIZCHIP_CREG_BLOCK) |
| Retransmission Counter Register address [R=W][0x08]. More... | |
| #define | _SLRTR_ (_W6100_IO_BASE_ + (0x4208 << 8) + WIZCHIP_CREG_BLOCK) |
| SOCKET-less Retransmission Time Register address [R=W][0x07D0]. More... | |
| #define | _SLRCR_ (_W6100_IO_BASE_ + (0x420C << 8) + WIZCHIP_CREG_BLOCK) |
| SOCKET-less Retransmission Count Register address [R=W][0x00]. More... | |
| #define | _SLHOPR_ (_W6100_IO_BASE_ + (0x420F << 8) + WIZCHIP_CREG_BLOCK) |
| SOCKET-less Hop Limit Register address [R=W][0x80]. More... | |
| #define | _Sn_MR_(N) (_W6100_IO_BASE_ + (0x0000 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| Socket Mode Register Address [R=W][0x00]. More... | |
| #define | _Sn_PSR_(N) (_W6100_IO_BASE_ + (0x0004 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKET n Prefer Source IPv6 Address Register Address [R=W][0x00]. More... | |
| #define | _Sn_CR_(N) (_W6100_IO_BASE_ + (0x0010 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| Socket Command Register Address [RW,AC][0x00]. More... | |
| #define | _Sn_IR_(N) (_W6100_IO_BASE_ + (0x0020 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn Interrupt Register Address [RO][0x00]. More... | |
| #define | _Sn_IMR_(N) (_W6100_IO_BASE_ + (0x0024 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn Interrupt Mask Register Address [R=W][0xFF]. More... | |
| #define | _Sn_IRCLR_(N) (_W6100_IO_BASE_ + (0x0028 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn Interrupt Clear Register Address [WO][0x00]. More... | |
| #define | _Sn_SR_(N) (_W6100_IO_BASE_ + (0x0030 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn Status Register Address [RO][0x00]. More... | |
| #define | _Sn_ESR_(N) (_W6100_IO_BASE_ + (0x0031 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn Extension Status Register Address [RO][0x00]. More... | |
| #define | _Sn_PNR_(N) (_W6100_IO_BASE_ + (0x0100 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn IP Protocol Number(PN) Register Address [R/W][0x0000]. More... | |
| #define | _Sn_NHR_(N) (_Sn_PNR_(N)) |
| Refer to _Sn_PNR_. More... | |
| #define | _Sn_TOSR_(N) (_W6100_IO_BASE_ + (0x0104 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn IPv4 Type of Service(TOS) Register Address [R=W][0x00]. More... | |
| #define | _Sn_TTLR_(N) (_W6100_IO_BASE_ + (0x0108 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn IP Time to live(TTL) Register Address [R=W][0x80]. More... | |
| #define | _Sn_HOPR_(N) (_Sn_TTLR_(N)) |
| Refer to _Sn_TTLR_. More... | |
| #define | _Sn_FRGR_(N) (_W6100_IO_BASE_ + (0x010C << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn Fragment Register Address [R=W][0x4000]. More... | |
| #define | _Sn_MSSR_(N) (_W6100_IO_BASE_ + (0x0110 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn Maximum Segment Size(MSS) Register Address [RW][0x0000]. More... | |
| #define | _Sn_PORTR_(N) (_W6100_IO_BASE_ + (0x0114 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn Source Port Register Address [R=W][0x0000]. More... | |
| #define | _Sn_DHAR_(N) (_W6100_IO_BASE_ + (0x0118 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn Destination Hardware Address Register Address [RW][00:00:00:00:00:00]. More... | |
| #define | _Sn_DIPR_(N) (_W6100_IO_BASE_ + (0x0120 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn Destination IPv4 Address Register Address [RW][0.0.0.0]. More... | |
| #define | _Sn_DIP4R_(N) (_Sn_DIPR_(N)) |
| Refer to _Sn_DIPR_. More... | |
| #define | _Sn_DIP6R_(N) (_W6100_IO_BASE_ + (0x0130 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn Destination IPv6 Address Register Address [RW][::]. More... | |
| #define | _Sn_DPORTR_(N) (_W6100_IO_BASE_ + (0x0140 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn Destination Port Register Address [RW][0x0000]. More... | |
| #define | _Sn_MR2_(N) (_W6100_IO_BASE_ + (0x0144 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn Mode Register 2 Address [R=W][0x00]. More... | |
| #define | _Sn_RTR_(N) (_W6100_IO_BASE_ + (0x0180 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn Retransmission Time Register Address [R=W][0x0000]. More... | |
| #define | _Sn_RCR_(N) (_W6100_IO_BASE_ + (0x0184 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn Retransmission Count Register Address [R=W][0x00]. More... | |
| #define | _Sn_KPALVTR_(N) (_W6100_IO_BASE_ + (0x0188 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn Keep Alive Time Register Address [R=W][0x00]. More... | |
| #define | _Sn_TX_BSR_(N) (_W6100_IO_BASE_ + (0x0200 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn TX Buffer Size Register Address [R=W][0x02]. More... | |
| #define | _Sn_TX_FSR_(N) (_W6100_IO_BASE_ + (0x0204 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn TX Free Buffer Size Register Address [RO][0x0800]. More... | |
| #define | _Sn_TX_RD_(N) (_W6100_IO_BASE_ + (0x0208 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKET TX Memory Read Pointer Register Address[R][0x0000]. More... | |
| #define | _Sn_TX_WR_(N) (_W6100_IO_BASE_ + (0x020C << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn TX Memory Write Pointer Register Address [RW][0x0000]. More... | |
| #define | _Sn_RX_BSR_(N) (_W6100_IO_BASE_ + (0x0220 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn RX Buffer Size Register Address [R=W][0x02]. More... | |
| #define | _Sn_RX_RSR_(N) (_W6100_IO_BASE_ + (0x0224 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn RX Received Size Register Address [RO][0x0000]. More... | |
| #define | _Sn_RX_RD_(N) (_W6100_IO_BASE_ + (0x0228 << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKET RX Memory Read Pointer Register Address[R][0x0000]. More... | |
| #define | _Sn_RX_WR_(N) (_W6100_IO_BASE_ + (0x022C << 8) + WIZCHIP_SREG_BLOCK(N)) |
| SOCKETn TX Memory Write Pointer Register Address [RW][0x0000]. More... | |
| #define | SYSR_CHPL (1 << 7) |
| CHIP Lock staus bit of _SYSR_. More... | |
| #define | SYSR_NETL (1 << 6) |
| NET Lock status bit of _SYSR_. More... | |
| #define | SYSR_PHYL (1 << 5) |
| PHY Lock status bit of _SYSR_. Refer to _PHYLCKR_. More... | |
| #define | SYSR_IND (1 << 5) |
| Parallel Bus Mode bit of _SYSR_. More... | |
| #define | SYSR_SPI (1 << 0) |
| SPI I/F Mode bit of _SYSR_. More... | |
| #define | SYCR0_RST (0x00) |
| RST bit of _SYCR0_. More... | |
| #define | SYCR1_IEN (1 << 7) |
| IEN bit of _SYCR1_. More... | |
| #define | SYCR1_CLKSEL (1 << 0) |
| System Clock select mask bit of _SYCR1_. More... | |
| #define | SYCR1_CLKSEL_25M 1 |
| System Clock - 25MHz. More... | |
| #define | SYCR1_CLKSEL_100M 0 |
| System Clock - 100MHz. More... | |
| #define | IR_WOL (1<<7) |
| WOL bit of _IR_. More... | |
| #define | IR_UNR6 (1<<4) |
| UNR6 bit of _IR_. More... | |
| #define | IR_IPCONF (1<<2) |
| IPCONF bit of _IR_. More... | |
| #define | IR_UNR4 (1<<1) |
| UNR4 bit of _IR_. More... | |
| #define | IR_PTERM (1<<0) |
| PTERM bit of _IR_. More... | |
| #define | SIR_INT(N) (1<<N) |
| N-th INT bit of @ref _SIR_. More... | |
| #define | SLIR_TOUT (1<<7) |
| TOUT bit of _SLIR_. More... | |
| #define | SLIR_ARP4 (1<<6) |
| ARP4 bit of _SLIR_. More... | |
| #define | SLIR_PING4 (1<<5) |
| PING4 bit of _SLIR_. More... | |
| #define | SLIR_ARP6 (1<<4) |
| ARP6 bit of _SLIR_. More... | |
| #define | SLIR_PING6 (1<<3) |
| PING6 bit of _SLIR_. More... | |
| #define | SLIR_NS (1<<2) |
| NS bit of _SLIR_. More... | |
| #define | SLIR_RS (1<<1) |
| RS bit of _SLIR_. More... | |
| #define | SLIR_RA (1<<0) |
| ICMPv6 RA Received Interrupt. More... | |
| #define | PSR_AUTO (0x00) |
| Select the source IPv6 address of the packet sent by _SLCR_ or _Sn_CR_ to AUTO. More... | |
| #define | PSR_LLA (0x02) |
| Select the source IP address of the packet sent by _SLCR_ or _Sn_CR_ to _LLAR_. More... | |
| #define | PSR_GUA (0x03) |
| Select the source IP address of the packet sent by _SLCR_ or _Sn_CR_ to _GUAR_. More... | |
| #define | SLCR_ARP4 (1<<6) |
| IPv4 ARP Command. More... | |
| #define | SLCR_PING4 (1<<5) |
| IPv4 PING Command. More... | |
| #define | SLCR_ARP6 (1<<4) |
| IPv6 ARP Command. More... | |
| #define | SLCR_PING6 (1<<3) |
| IPv6 PING Command. More... | |
| #define | SLCR_NS (1<<2) |
| IPv6 DAD(Duplicate Address Detection) NS Command. More... | |
| #define | SLCR_RS (1<<1) |
| IPv6 Auto-configuration RS Command. More... | |
| #define | SLCR_UNA (1<<0) |
| IPv6 Unsolicited NA Command. More... | |
| #define | PHYSR_CAB (1<<7) |
| CAB mask bit. More... | |
| #define | PHYSR_CAB_OFF (1<<7) |
| Ethernet Cable Off. More... | |
| #define | PHYSR_CAB_ON (0<<7) |
| Ethernet PHY Cable On. More... | |
| #define | PHYSR_MODE (7<<3) |
| Mask bits of _PHYSR_. More... | |
| #define | PHYSR_MODE_AUTO (0<<3) |
| PHY Mode - AUTO. More... | |
| #define | PHYSR_MODE_100F (4<<3) |
| PHY Mode - 100F. More... | |
| #define | PHYSR_MODE_100H (5<<3) |
| PHY Mode - 100H. More... | |
| #define | PHYSR_MODE_10F (6<<3) |
| PHY Mode - 10F. More... | |
| #define | PHYSR_MODE_10H (7<<3) |
| PHY Mode - 10H. More... | |
| #define | PHYSR_DPX (1<<2) |
| DPX mask bit of _PHYSR_. More... | |
| #define | PHYSR_DPX_HALF (1<<2) |
| PHY Duplex - HALF. More... | |
| #define | PHYSR_DPX_FULL (0<<2) |
| PHY Duplex - FULL. More... | |
| #define | PHYSR_SPD (1<<1) |
| SPD mask bit of _PHYSR_. More... | |
| #define | PHYSR_SPD_10M (1<<1) |
| PHY Speed - 10M. More... | |
| #define | PHYSR_SPD_100M (0<<1) |
| PHY Speed - 100M. More... | |
| #define | PHYSR_LNK (1<<0) |
| LNK mask bit of _PHYSR_. More... | |
| #define | PHYSR_LNK_UP (1<<0) |
| PHY Link - Up. More... | |
| #define | PHYSR_LNK_DOWN (0<<0) |
| PHY Link - Down. More... | |
| #define | PHYACR_READ (0x02) |
| Read a value from the Ethernet PHY register specified by _PHYRAR_. The read value can be checked by _PHYDOR_. More... | |
| #define | PHYACR_WRITE (0x01) |
| Write _PHYDIR_ to the Ethernet PHY register specified by _PHYRAR_. More... | |
| #define | PHYDIVR_32 (0x00) |
| PHY's MDC clock is the divided the system clock by 32. More... | |
| #define | PHYDIVR_64 (0x01) |
| PHY's MDC clock is the divided system clock by 64. More... | |
| #define | PHYDIVR_128 (0xFF) |
| PHY's MDC clock is the divided system clock by 128. More... | |
| #define | PHYCR0_AUTO (0x00) |
| PHY Operation Mode - Auto Negotiation. More... | |
| #define | PHYCR0_100F (0x04) |
| PHY Operation Mode - 100F. More... | |
| #define | PHYCR0_100H (0x05) |
| PHY Operation Mode - 100H. More... | |
| #define | PHYCR0_10F (0x06) |
| PHY Operation Mode - 10F. More... | |
| #define | PHYCR0_10H (0x07) |
| PHY Operation Mode - 10H. More... | |
| #define | PHYCR1_PWDN (1<<5) |
| PHY function - Power Down. More... | |
| #define | PHYCR1_TE (1<<3) |
| PHY function - 10Base-TE Mode. More... | |
| #define | PHYCR1_RST (1<<0) |
| PHY function - HW Reset. More... | |
| #define | NETxMR_UNRB (1<<3) |
| UDP Unreachable Packet Block. More... | |
| #define | NETxMR_PARP (1<<2) |
| PING ARP Request. More... | |
| #define | NETxMR_RSTB (1<<1) |
| TCP Reset Packet Block. More... | |
| #define | NETxMR_PB (1<<0) |
| PING Reply Block. More... | |
| #define | NETMR_ANB (1<<5) |
| All-node Multicating PING Reply Block. More... | |
| #define | NETMR_M6B (1<<4) |
| Solicited Multicasting PING Reply Block. More... | |
| #define | NETMR_WOL (1<<2) |
| Wake On LAN mode. More... | |
| #define | NETMR_IP6B (1<<1) |
| IPv6 Packet Block. More... | |
| #define | NETMR_IP4B (1<<0) |
| IPv4 Packet Block. More... | |
| #define | NETMR2_DHAS (1<<7) |
| Destination Hardware Address Select. More... | |
| #define | NETMR2_DHAS_ARP (1<<7) |
| Destination Hardware Address Select - ARP. More... | |
| #define | NETMR2_DHAS_ETH (0<<7) |
| Destination Hardware Address Select - Ethernet Frame. More... | |
| #define | NETMR2_PPPoE (1<<0) |
| PPPoE Mode. More... | |
| #define | ICMP6BLKR_PING6 (1<<4) |
| ICMPv6 PING Block. More... | |
| #define | ICMP6BLKR_MLD (1<<3) |
| ICMPv6 MLD Block. More... | |
| #define | ICMP6BLKR_RA (1<<2) |
| ICMPv6 RA Block. More... | |
| #define | ICMP6BLKR_NA (1<<1) |
| ICMPv6 NA Block. More... | |
| #define | ICMP6BLKR_NS (1<<0) |
| ICMPv6 NS Block. More... | |
| #define | Sn_MR_MULTI (1<<7) |
| UDP Multicasting. More... | |
| #define | Sn_MR_MF (1<<7) |
| MAC Filter. More... | |
| #define | Sn_MR_BRDB (1<<6) |
| Broadcasting packet block. More... | |
| #define | Sn_MR_FPSH (1<<6) |
| Force PUSH flag. More... | |
| #define | Sn_MR_ND (1<<5) |
| No Delayed Ack. More... | |
| #define | Sn_MR_MC (1<<5) |
| IGMP version for IPv4 Multicasting. More... | |
| #define | Sn_MR_SMB (1<<5) |
| Solicited Mulitcast Block. More... | |
| #define | Sn_MR_MMB (1<<5) |
| UDP4 Multicast Block. More... | |
| #define | Sn_MR_MMB4 (Sn_MR_MMB) |
| #define | Sn_MR_UNIB (1<<4) |
| Unicast Block. More... | |
| #define | Sn_MR_MMB6 (1<<4) |
| UDP6 Multicast Block. More... | |
| #define | Sn_MR_CLOSE (0x00) |
| SOCKETn Closed. More... | |
| #define | Sn_MR_TCP (0x01) |
| IPv4 TCP mode. More... | |
| #define | Sn_MR_TCP4 (Sn_MR_TCP) |
| Refer to Sn_MR_TCP. More... | |
| #define | Sn_MR_UDP (0x02) |
| IPv4 UDP mode. More... | |
| #define | Sn_MR_UDP4 (Sn_MR_UDP) |
| Refer to Sn_MR_UDP. More... | |
| #define | Sn_MR_IPRAW (0x03) |
| IPv4 RAW mode. More... | |
| #define | Sn_MR_IPRAW4 (Sn_MR_IPRAW) |
| Refer to Sn_MR_IPRAW. More... | |
| #define | Sn_MR_MACRAW (0x07) |
| MACRAW mode. More... | |
| #define | Sn_MR_TCP6 (0x09) |
| IPv6 TCP mode. More... | |
| #define | Sn_MR_UDP6 (0x0A) |
| IPv6 UDP mode. More... | |
| #define | Sn_MR_IPRAW6 (0x0B) |
| IPv6 RAW mode. More... | |
| #define | Sn_MR_TCPD (0x0D) |
| Both IPv4 & IPv6 TCP mode (TCP dual mode) More... | |
| #define | Sn_MR_UDPD (0x0E) |
| UDP Dual mode. More... | |
| #define | Sn_CR_OPEN (0x01) |
| Initialize or Open SOCKETn. More... | |
| #define | Sn_CR_LISTEN (0x02) |
| Wait a connection request in TCP SERVER mode. More... | |
| #define | Sn_CR_CONNECT (0x04) |
| Send a connection request in TCP CLIENT mode. More... | |
| #define | Sn_CR_CONNECT6 (0x84) |
| Send connection request in TCP CLIENT mode. More... | |
| #define | Sn_CR_DISCON (0x08) |
| Send a disconnect request in TCP mode. More... | |
| #define | Sn_CR_CLOSE (0x10) |
| Release or Close SOCKETn. More... | |
| #define | Sn_CR_SEND (0x20) |
| Send Data. More... | |
| #define | Sn_CR_SEND6 (0xA0) |
| Send Data. More... | |
| #define | Sn_CR_SEND_KEEP (0x22) |
| Send keep alive message. More... | |
| #define | Sn_CR_RECV (0x40) |
| Receive data. More... | |
| #define | Sn_IR_SENDOK (0x10) |
| SEND OK Interrupt. More... | |
| #define | Sn_IR_TIMEOUT (0x08) |
| TIMEOUT Interrupt. More... | |
| #define | Sn_IR_RECV (0x04) |
| RECV Interrupt. More... | |
| #define | Sn_IR_DISCON (0x02) |
| DISCON Interrupt. More... | |
| #define | Sn_IR_CON (0x01) |
| CONNECT Interrupt. More... | |
| #define | SOCK_CLOSED (0x00) |
| SOCKETn Closed status. More... | |
| #define | SOCK_INIT (0x13) |
| TCP SOCKETn initialized status. More... | |
| #define | SOCK_LISTEN (0x14) |
| TCP SOCKETn Listen status. More... | |
| #define | SOCK_SYNSENT (0x15) |
| TCP Connection Request status. More... | |
| #define | SOCK_SYNRECV (0x16) |
| TCP Connection Accept status. More... | |
| #define | SOCK_ESTABLISHED (0x17) |
| TCP SOCKETn Established status. More... | |
| #define | SOCK_FIN_WAIT (0x18) |
| TCP SOCKETn Closing status. More... | |
| #define | SOCK_TIME_WAIT (0x1B) |
| TCP SOCKETn Closing status. More... | |
| #define | SOCK_CLOSE_WAIT (0x1C) |
| TCP SOCKETn Half Closing staus. More... | |
| #define | SOCK_LAST_ACK (0x1D) |
| TCP SOCKETn Closing status. More... | |
| #define | SOCK_UDP (0x22) |
| UDP SOCKETn status. More... | |
| #define | SOCK_IPRAW4 (0x32) |
| IPRAW4 SOCKETn mode. More... | |
| #define | SOCK_IPRAW (SOCK_IPRAW4) |
| Refer to SOCK_IPRAW4. More... | |
| #define | SOCK_IPRAW6 (0x33) |
| IPRAW6 SOCKETn mode. More... | |
| #define | SOCK_MACRAW (0x42) |
| MACRAW SOCKETn mode. More... | |
| #define | Sn_ESR_TCPM (1<<2) |
| SOCKETn Extended Status : TCP Mode. More... | |
| #define | Sn_ESR_TCPM_IPV4 (0<<2) |
| TCP SOCKETn IP version - IPv4. More... | |
| #define | Sn_ESR_TCPM_IPV6 (1<<2) |
| TCP SOCKETn IP version - IPv6. More... | |
| #define | Sn_ESR_TCPOP (1<<1) |
| SOCKETn Extended Status : TCP Operation Mode. More... | |
| #define | Sn_ESR_TCPOP_SVR (0<<1) |
| TCP SOCKETn Operation Mode - TCP SERVER More... | |
| #define | Sn_ESR_TCPOP_CLT (1<<1) |
| TCP SOCKETn Operation Mode - TCP CLIENT More... | |
| #define | Sn_ESR_IP6T (1<<0) |
| SOCKETn Extended Status : Source IPv6 Address Type. More... | |
| #define | Sn_ESR_IP6T_LLA (0<<0) |
| Source IPv6 Address Type - LLA. More... | |
| #define | Sn_ESR_IP6T_GUA (1<<0) |
| Source IPv6 Address Type - LLA. More... | |
| #define | Sn_MR2_DHAM (1<<1) |
| Destination Hardware Address Mode. More... | |
| #define | Sn_MR2_DHAM_AUTO (0<<1) |
| Destination Hardware Address Mode - AUTO. More... | |
| #define | Sn_MR2_DHAM_MANUAL (1<<1) |
| Destination Hardware Address Mode - MANUAL. More... | |
| #define | Sn_MR2_FARP (1<<0) |
| Force ARP. More... | |
| #define | PHYRAR_BMCR (0x00) |
| Basic Mode Control Register of Ethernet PHY [RW][0x3100]. More... | |
| #define | PHYRAR_BMSR (0x01) |
| Basic Mode Status Register of Ethernet PHY [RO][0x7809]. More... | |
| #define | BMCR_RST (1<<15) |
| Ethernet PHY S/W Reset. More... | |
| #define | BMCR_LB (1<<14) |
| Ethernet PHY Loopback. More... | |
| #define | BMCR_SPD (1<<13) |
| Ethernet PHY Speed. More... | |
| #define | BMCR_ANE (1<<12) |
| Ethernet PHY Auto-Negotiation. More... | |
| #define | BMCR_PWDN (1<<11) |
| Ethernet PHY Power Down Mode. More... | |
| #define | BMCR_ISOL (1<<10) |
| Ethernet PHY Isolation Mode. More... | |
| #define | BMCR_REAN (1<<9) |
| Ethernet PHY Restart Auto-Negotiation. More... | |
| #define | BMCR_DPX (1<<8) |
| Ethernet PHY Duplex. More... | |
| #define | BMCR_COLT (1<<7) |
| Ethernet PHY Collision Test. More... | |
| #define | BMSR_100_T4 (1<<15) |
| Ethernet PHY 100 Base-T4 capable. More... | |
| #define | BMSR_100_FDX (1<<14) |
| Ethernet PHY 100 Base-TX Full-Duplex capable. More... | |
| #define | BMSR_100_HDX (1<<13) |
| Ethernet PHY 100 Base-TX Half-Duplex capable. More... | |
| #define | BMSR_10_FDX (1<<12) |
| Ethernet PHY 10 Base-T Full-Duplex capable. More... | |
| #define | BMSR_10_HDX (1<<11) |
| Ethernet PHY 10 Base-T Half-Duplex capable. More... | |
| #define | BMSR_MF_SUP (1<<6) |
| Ethernet PHY Management Frame preamble suppression. More... | |
| #define | BMSR_AN_COMP (1<<5) |
| Ethernet PHY Auto-Negotiation Complete. More... | |
| #define | BMSR_REMOTE_FAULT (1<<4) |
| Ethernet PHY Remote Fault. More... | |
| #define | BMSR_AN_ABILITY (1<<3) |
| Ethernet PHY Auto-Negotiation Ability. More... | |
| #define | BMSR_LINK_STATUS (1<<2) |
| Ethernet PHY Link Status. More... | |
| #define | BMSR_JABBER_DETECT (1<<1) |
| Ethernet PHY Jabber Detect. More... | |
| #define | BMSR_EXT_CAPA (1<<0) |
| Ethernet PHY Extended capability. More... | |
| #define | WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._e_n_t_e_r_() |
| Enter a critical section. More... | |
| #define | WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._e_x_i_t_() |
| Enter a critical section. More... | |
| #define | getCIDR() ((((uint16_t)WIZCHIP_READ(_CIDR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_CIDR_,1))) |
| #define | getVER() ((((uint16_t)WIZCHIP_READ(_VER_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_VER_,1))) |
| #define | getSYSR() WIZCHIP_READ(_SYSR_) |
| #define | getSYCR0() WIZCHIP_READ(_SYCR0_) |
| #define | setSYCR0(sycr0) WIZCHIP_WRITE(_SYCR0_, (sycr0)) |
| #define | getSYCR1() WIZCHIP_READ(_SYCR1_) |
| #define | setSYCR1(sycr1) WIZCHIP_WRITE(_SYCR1_, (sycr1)) |
| #define | getTCNTR() ((((uint16_t)WIZCHIP_READ(_TCNTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_TCNTR_,1))) |
| #define | setTCNTRCLR(tcntrclr) WIZCHIP_WRITE(_TCNTRCLR_,(tcntrclr)) |
| #define | getIR() WIZCHIP_READ(_IR_) |
| #define | getSIR() WIZCHIP_READ(_SIR_) |
| #define | getSLIR() WIZCHIP_READ(_SLIR_) |
| #define | setIMR(imr) WIZCHIP_WRITE(_IMR_,(imr)) |
| #define | getIMR() WIZCHIP_READ(_IMR_) |
| #define | setIRCLR(irclr) WIZCHIP_WRITE(_IRCLR_,(irclr)) |
| #define | setIR(ir) setIRCLR(ir) |
| #define | setSIMR(simr) WIZCHIP_WRITE(_SIMR_,(simr)) |
| #define | getSIMR() WIZCHIP_READ(_SIMR_) |
| #define | setSLIMR(slimr) WIZCHIP_WRITE(_SLIMR_,(slimr)) |
| #define | getSLIMR() WIZCHIP_READ(_SLIMR_) |
| #define | setSLIRCLR(slirclr) WIZCHIP_WRITE(_SLIRCLR_,(slirclr)) |
| #define | setSLIR(slir) setSLIRCLR(slir) |
| #define | setSLPSR(slpsr) WIZCHIP_WRITE(_SLPSR_,(slpsr)) |
| #define | getSLPSR() WIZCHIP_READ(_SLPSR_) |
| #define | setSLCR(slcr) WIZCHIP_WRITE(_SLCR_,(slcr)) |
| #define | getSLCR() WIZCHIP_READ(_SLCR_) |
| #define | getPHYSR() WIZCHIP_READ(_PHYSR_) |
| #define | setPHYRAR(phyrar) WIZCHIP_WRITE(_PHYRAR_,(phyrar)) |
| #define | getPHYRAR() WIZCHIP_READ(_PHYRAR_) |
| #define | setPHYDIR(phydir) |
| #define | getPHYDOR() ((((uint16_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PHYDOR_,1))) << 8) + WIZCHIP_READ(_PHYDOR_)) |
| #define | setPHYACR(phyacr) WIZCHIP_WRITE(_PHYACR_,(phyacr)) |
| #define | getPHYACR() WIZCHIP_READ(_PHYACR_) |
| #define | setPHYDIVR(phydivr) WIZCHIP_WRITE(_PHYDIVR_,(phydivr)) |
| #define | getPHYDIVR() WIZCHIP_READ(_PHYDIVR_) |
| #define | setPHYCR0(phycr0) WIZCHIP_WRITE(_PHYCR0_,(phycr0)) |
| #define | setPHYCR1(phycr1) WIZCHIP_WRITE(_PHYCR1_,(phycr1)) |
| #define | getPHYCR1() WIZCHIP_READ(_PHYCR1_) |
| #define | setNET4MR(net4mr) WIZCHIP_WRITE(_NET4MR_,(net4mr)) |
| #define | setNET6MR(net6mr) WIZCHIP_WRITE(_NET6MR_,(net6mr)) |
| #define | setNETMR(netmr) WIZCHIP_WRITE(_NETMR_,(netmr)) |
| #define | setNETMR2(netmr2) WIZCHIP_WRITE(_NETMR2_,(netmr2)) |
| #define | getNET4MR() WIZCHIP_READ(_NET4MR_) |
| #define | getNET6MR() WIZCHIP_READ(_NET6MR_) |
| #define | getNETMR() WIZCHIP_READ(_NETMR_) |
| #define | getNETMR2() WIZCHIP_READ(_NETMR2_) |
| #define | setPTMR(ptmr) WIZCHIP_WRITE(_PTMR_, (ptmr)) |
| #define | getPTMR() WIZCHIP_READ(_PTMR_) |
| #define | setPMNR(pmnr) WIZCHIP_WRITE(_PMNR_, (pmnr)) |
| #define | getPMNR() WIZCHIP_READ(_PMNR_) |
| #define | setPHAR(phar) WIZCHIP_WRITE_BUF(_PHAR_,(phar),6) |
| #define | getPHAR(phar) WIZCHIP_READ_BUF(_PHAR_,(phar),6) |
| #define | setPSIDR(psidr) |
| #define | getPSIDR() ((((uint16_t)WIZCHIP_READ(_PSIDR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PSIDR_,1))) |
| #define | setPMRUR(pmrur) |
| #define | getPMRUR() ((((uint16_t)WIZCHIP_READ(_PMRUR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PMRUR_,1))) |
| #define | setSHAR(shar) WIZCHIP_WRITE_BUF(_SHAR_,(shar),6) |
| #define | getSHAR(shar) WIZCHIP_READ_BUF(_SHAR_,(shar),6) |
| #define | setGAR(gar) WIZCHIP_WRITE_BUF(_GAR_,(gar),4) |
| #define | getGAR(gar) WIZCHIP_READ_BUF(_GAR_,(gar),4) |
| #define | setGA4R(ga4r) setGAR(ga4r) |
| #define | getGA4R(ga4r) getGAR(ga4r) |
| #define | setSUBR(subr) WIZCHIP_WRITE_BUF(_SUBR_,(subr),4) |
| #define | getSUBR(subr) WIZCHIP_READ_BUF(_SUBR_,(subr),4) |
| #define | setSUB4R(sub4r) setSUBR(sub4r) |
| #define | getSUB4R(sub4r) getSUBR(sub4r) |
| #define | setSIPR(sipr) WIZCHIP_WRITE_BUF(_SIPR_,(sipr),4) |
| #define | getSIPR(sipr) WIZCHIP_READ_BUF(_SIPR_,(sipr),4) |
| #define | setLLAR(llar) WIZCHIP_WRITE_BUF(_LLAR_,(llar),16) |
| #define | getLLAR(llar) WIZCHIP_READ_BUF(_LLAR_,(llar),16) |
| #define | setGUAR(guar) WIZCHIP_WRITE_BUF(_GUAR_,(guar),16) |
| #define | getGUAR(guar) WIZCHIP_READ_BUF(_GUAR_,(guar),16) |
| #define | setSUB6R(sub6r) WIZCHIP_WRITE_BUF(_SUB6R_,(sub6r),16) |
| #define | getSUB6R(sub6r) WIZCHIP_READ_BUF(_SUB6R_,(sub6r),16) |
| #define | setGA6R(ga6r) WIZCHIP_WRITE_BUF(_GA6R_,(ga6r),16) |
| #define | getGA6R(ga6r) WIZCHIP_READ_BUF(_GA6R_,(ga6r),16) |
| #define | setSLDIPR(sldipr) WIZCHIP_WRITE_BUF(_SLDIPR_,(sldipr),4) |
| #define | setSLDIP4R(sldip4r) setSLDIPR((sldip4r)) |
| #define | getSLDIPR(sldipr) WIZCHIP_READ_BUF(_SLDIPR_,(sldipr),4) |
| #define | getSLDIP4R(sldip4r) getSLDIPR((sldip4r)) |
| #define | setSLDIP6R(sldip6r) WIZCHIP_WRITE_BUF(_SLDIP6R_, (sldip6r),16) |
| #define | getSLDIP6R(sldip6r) WIZCHIP_READ_BUF(_SLDIP6R_,(sldip6r),16) |
| #define | getSLDHAR(sldhar) WIZCHIP_READ_BUF(_SLDHAR_,(sldhar),6) |
| #define | setPINGIDR(pingidr) |
| #define | getPINGIDR() (((int16_t)(WIZCHIP_READ(_PINGIDR_) << 8)) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PINGIDR_,1))) |
| #define | setPINGSEQR(pingseqr) |
| #define | getPINGSEQR() (((int16_t)(WIZCHIP_READ(_PINGSEQR_) << 8)) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_PINGSEQR_,1))) |
| #define | getUIPR(uipr) WIZCHIP_READ_BUF(_UIPR_, (uipr), 4) |
| #define | getUIP4R(uip4r) getUIPR(uip4r) |
| #define | getUPORTR() ((((uint16_t)WIZCHIP_READ(_UPORTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_UPORTR_,1))) |
| #define | getUPORT4R() getUPORTR() |
| #define | getUIP6R(uip6r) WIZCHIP_READ_BUF(_UIP6R_,(uip6r),16) |
| #define | getUPORT6R(uport6r) ((((uint16_t)WIZCHIP_READ(_UPORT6R_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_UPORT6R_,1))) |
| #define | setINTPTMR(intptmr) |
| #define | getINTPTMR() ((((uint16_t)WIZCHIP_READ(_INTPTMR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_INTPTMR_,1))) |
| #define | getPLR() WIZCHIP_READ(_PLR_) |
| #define | getPFR() WIZCHIP_READ(_PFR_) |
| #define | getVLTR() |
| #define | getPLTR() |
| #define | getPAR(par) WIZCHIP_READ_BUF(_PAR_, (par), 16) |
| #define | setICMP6BLKR(icmp6blkr) WIZCHIP_WRITE(_ICMP6BLKR_,(icmp6blkr)) |
| #define | getICMP6BLKR() WIZCHIP_READ(_ICMP6BLKR_) |
| #define | setCHPLCKR(chplckr) WIZCHIP_WRITE(_CHPLCKR_, (chplckr)) |
| #define | getCHPLCKR() ((getSYSR() & SYSR_CHPL) >> 7) |
| #define | CHIPLOCK() setCHPLCKR(0xFF) |
| #define | CHIPUNLOCK() setCHPLCKR(0xCE) |
| #define | setNETLCKR(netlckr) WIZCHIP_WRITE(_NETLCKR_, (netlckr)) |
| #define | getNETLCKR() ((getSYSR() & SYSR_NETL) >> 6) |
| #define | NETLOCK() setNETLCKR(0xC5) |
| #define | NETUNLOCK() setNETLCKR(0x3A) |
| #define | setPHYLCKR(phylckr) WIZCHIP_WRITE(_PHYLCKR_,(phylckr)) |
| #define | getPHYLCKR() ((getSYSR() & SYSR_PHYL) >> 5) |
| #define | PHYLOCK() setPHYLCKR(0xFF) |
| #define | PHYUNLOCK() setPHYLCKR(0x53) |
| #define | setRTR(rtr) |
| #define | getRTR() ((((uint16_t)WIZCHIP_READ(_RTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1))) |
| #define | setRCR(rcr) WIZCHIP_WRITE(_RCR_,(rcr)) |
| #define | getRCR() WIZCHIP_READ(_RCR_) |
| #define | setSLRTR(slrtr) |
| #define | getSLRTR() ((((uint16_t)WIZCHIP_READ(_SLRTR_)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_SLRTR_,1))) |
| #define | setSLRCR(slrcr) WIZCHIP_WRITE(_SLRCR_,(slrcr)) |
| #define | getSLRCR() WIZCHIP_READ(_SLRCR_) |
| #define | setSLHOPR(slhopr) WIZCHIP_WRITE(_SLHOPR_,(slhopr)) |
| #define | getSLHOPR() WIZCHIP_READ(_SLHOPR_) |
| #define | setSn_MR(sn, mr) WIZCHIP_WRITE(_Sn_MR_(sn),(mr)) |
| #define | getSn_MR(sn) WIZCHIP_READ(_Sn_MR_(sn)) |
| #define | setSn_PSR(sn, psr) WIZCHIP_WRITE(_Sn_PSR_(sn),(psr)) |
| #define | getSn_PSR(sn) WIZCHIP_READ(_Sn_PSR_(sn)) |
| #define | setSn_CR(sn, cr) WIZCHIP_WRITE(_Sn_CR_(sn),(cr)) |
| #define | getSn_CR(sn) WIZCHIP_READ(_Sn_CR_(sn)) |
| #define | getSn_IR(sn) WIZCHIP_READ(_Sn_IR_(sn)) |
| #define | setSn_IMR(sn, imr) WIZCHIP_WRITE(_Sn_IMR_(sn),(imr)) |
| #define | getSn_IMR(sn) WIZCHIP_READ(_Sn_IMR_(sn)) |
| #define | setSn_IRCLR(sn, irclr) WIZCHIP_WRITE(_Sn_IRCLR_(sn),(irclr)) |
| #define | setSn_IR(sn, ir) setSn_IRCLR(sn,(ir)) |
| #define | getSn_SR(sn) WIZCHIP_READ(_Sn_SR_(sn)) |
| #define | getSn_ESR(sn) WIZCHIP_READ(_Sn_ESR_(sn)) |
| #define | setSn_PNR(sn, pnr) WIZCHIP_WRITE(_Sn_PNR_(sn),(pnr)) |
| #define | setSn_NHR(sn, nhr) setSn_PNR(_Sn_PNR_(sn),(nhr)) |
| #define | getSn_PNR(sn) WIZCHIP_READ(_Sn_PNR_(sn)) |
| #define | getSn_NHR(sn) getSn_PNR(sn) |
| #define | setSn_TOSR(sn, tosr) WIZCHIP_WRITE(_Sn_TOSR_(sn),(tosr)) |
| #define | getSn_TOSR(sn) WIZCHIP_READ(_Sn_TOSR_(sn)) |
| #define | setSn_TTLR(sn, ttlr) WIZCHIP_WRITE(_Sn_TTLR_(sn),(ttlr)) |
| #define | getSn_TTLR(sn) WIZCHIP_READ(_Sn_TTLR_(sn)) |
| #define | setSn_HOPR(sn, hopr) setSn_TTLR(sn),(ttlr)) |
| #define | getSn_HOPR(sn) getSn_TTLR(sn) |
| #define | setSn_FRGR(sn, frgr) |
| #define | getSn_FRGR(sn, frgr) ((((uint16_t)WIZCHIP_READ(_Sn_FRGR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_FRGR_(sn),1))) |
| #define | setSn_MSSR(sn, mssr) |
| #define | getSn_MSSR(sn) ((((uint16_t)WIZCHIP_READ(_Sn_MSSR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_MSSR_(sn),1))) |
| #define | setSn_PORTR(sn, portr) |
| #define | getSn_PORTR(sn) ((((uint16_t)WIZCHIP_READ(_Sn_PORTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_PORTR_(sn),1))) |
| #define | setSn_DHAR(sn, dhar) WIZCHIP_WRITE_BUF(_Sn_DHAR_(sn),(dhar),6) |
| #define | getSn_DHAR(sn, dhar) WIZCHIP_READ_BUF(_Sn_DHAR_(sn),(dhar),6) |
| #define | setSn_DIPR(sn, dipr) WIZCHIP_WRITE_BUF(_Sn_DIPR_(sn),(dipr),4) |
| #define | getSn_DIPR(sn, dipr) WIZCHIP_READ_BUF(_Sn_DIPR_(sn),(dipr),4) |
| #define | setSn_DIP4R(sn, dipr) setSn_DIPR(sn,(dipr)) |
| #define | getSn_DIP4R(sn, dipr) getSn_DIPR(sn,(dipr)) |
| #define | setSn_DIP6R(sn, dip6r) WIZCHIP_WRITE_BUF(_Sn_DIP6R_(sn),(dip6r),16) |
| #define | getSn_DIP6R(sn, dip6r) WIZCHIP_READ_BUF(_Sn_DIP6R_(sn),(dip6r),16) |
| #define | setSn_DPORTR(sn, dportr) |
| #define | getSn_DPORTR(sn) ((((uint16_t)WIZCHIP_READ(_Sn_DPORTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_DPORTR_(sn),1))) |
| #define | setSn_MR2(sn, mr2) WIZCHIP_WRITE(_Sn_MR2_(sn),(mr2)) |
| #define | getSn_MR2(sn) WIZCHIP_READ(_Sn_MR2_(sn)) |
| #define | setSn_RTR(sn, rtr) |
| #define | getSn_RTR(sn) ((((uint16_t)WIZCHIP_READ(_Sn_RTR_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RTR_(sn),1))) |
| #define | setSn_RCR(sn, rcr) WIZCHIP_WRITE(_Sn_RCR_(sn),(rcr)) |
| #define | getSn_RCR(sn) WIZCHIP_READ(_Sn_RCR_(sn)) |
| #define | setSn_KPALVTR(sn, kpalvtr) WIZCHIP_WRITE(_Sn_KPALVTR_(sn),(kpalvtr)) |
| #define | getSn_KPALVTR(sn) WIZCHIP_READ(_Sn_KPALVTR_(sn)) |
| #define | setSn_TX_BSR(sn, tmsr) WIZCHIP_WRITE(_Sn_TX_BSR_(sn),(tmsr)) |
| #define | setSn_TXBUF_SIZE(sn, tmsr) setSn_TX_BSR(sn,(tmsr)) |
| #define | getSn_TX_BSR(sn) WIZCHIP_READ(_Sn_TX_BSR_(sn)) |
| #define | getSn_TXBUF_SIZE(sn) getSn_TX_BSR(sn) |
| #define | getSn_TxMAX(sn) (getSn_TX_BSR(sn) << 10) |
| #define | getSn_TX_RD(sn) ((((uint16_t)WIZCHIP_READ(_Sn_TX_RD_(sn))) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_RD_(sn),1))) |
| #define | setSn_TX_WR(sn, txwr) |
| #define | getSn_TX_WR(sn) (((uint16_t)WIZCHIP_READ(_Sn_TX_WR_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_TX_WR_(sn),1))) |
| #define | setSn_RX_BSR(sn, rmsr) WIZCHIP_WRITE(_Sn_RX_BSR_(sn),(rmsr)) |
| #define | setSn_RXBUF_SIZE(sn, rmsr) setSn_RX_BSR(sn,(rmsr)) |
| #define | getSn_RX_BSR(sn) WIZCHIP_READ(_Sn_RX_BSR_(sn)) |
| #define | getSn_RXBUF_SIZE(sn) getSn_RX_BSR(sn) |
| #define | getSn_RxMAX(sn) (getSn_RX_BSR(sn) <<10) |
| #define | setSn_RX_RD(sn, rxrd) |
| #define | getSn_RX_RD(sn) (((uint16_t)WIZCHIP_READ(_Sn_RX_RD_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_RD_(sn),1))) |
| #define | getSn_RX_WR(sn) (((uint16_t)WIZCHIP_READ(_Sn_RX_WR_(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_Sn_RX_WR_(sn),1))) |
Functions | |
| uint8_t | WIZCHIP_READ (uint32_t AddrSel) |
| It reads 1 byte value from a register. More... | |
| void | WIZCHIP_WRITE (uint32_t AddrSel, uint8_t wb) |
| It writes 1 byte value to a register. More... | |
| void | WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t *pBuf, datasize_t len) |
| It reads sequentail data from registers. More... | |
| void | WIZCHIP_WRITE_BUF (uint32_t AddrSel, uint8_t *pBuf, datasize_t len) |
| It writes sequential data to registers. More... | |
| datasize_t | getSn_TX_FSR (uint8_t sn) |
| datasize_t | getSn_RX_RSR (uint8_t s) |
| void | wiz_send_data (uint8_t sn, uint8_t *wizdata, datasize_t len) |
| It saves data to be sent in the SOCKETn TX buffer. More... | |
| void | wiz_recv_data (uint8_t sn, uint8_t *wizdata, datasize_t len) |
| It reads the received data from the SOCKETn RX buffer and copies the data to your system memory specified by wizdata. More... | |
| void | wiz_recv_ignore (uint8_t sn, datasize_t len) |
| It discards the received data in the SOCKETn RX buffer. More... | |
| void | wiz_mdio_write (uint8_t phyregaddr, uint16_t var) |
| Write data to the PHY via MDC/MDIO interface. More... | |
| uint16_t | wiz_mdio_read (uint8_t phyregaddr) |
| Read data from the PHY via MDC/MDIO interface. More... | |
W6100 HAL Header File.
Copyright (c) 2019, WIZnet Co., LTD.
Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Definition in file w6100.h.
| #define _W6100_SPI_READ_ (0x00 << 2) |
| #define _W6100_SPI_WRITE_ (0x01 << 2) |
| #define WIZCHIP_SREG_BLOCK | ( | N | ) | ((1+4*N)<<3) |
| #define WIZCHIP_TXBUF_BLOCK | ( | N | ) | ((2+4*N)<<3) |
| #define WIZCHIP_RXBUF_BLOCK | ( | N | ) | ((3+4*N)<<3) |
| #define WIZCHIP_OFFSET_INC | ( | ADDR, | |
| N | |||
| ) | (ADDR + (N<<8)) |
| #define IDM_AR0 ((_WIZCHIP_IO_BASE_ + 0x0000)) |
| #define IDM_AR1 ((_WIZCHIP_IO_BASE_ + 0x0001)) |
| #define IDM_BSR ((_WIZCHIP_IO_BASE_ + 0x0002)) |
| #define IDM_DR ((_WIZCHIP_IO_BASE_ + 0x0003)) |
| #define SYSR_CHPL (1 << 7) |
CHIP Lock staus bit of _SYSR_.
SYSR_CHPL indicates the lock status of _SYCR0_ and _SYCR1_.
1 : Lock
0 : unlock
| #define SYSR_NETL (1 << 6) |
NET Lock status bit of _SYSR_.
SYSR_NETL indicates the lock of network information registers such as _SHAR_, _GAR_, _SUBR_, _SIPR_, _LLAR_, _GUAR_, and _SUB6R_.
1 : Lock
0 : unlock
| #define SYSR_PHYL (1 << 5) |
PHY Lock status bit of _SYSR_. Refer to _PHYLCKR_.
SYSR_PHYL indicates the lock status of _PHYCR0_ and _PHYCR1_.
1 : Lock
0 : unlock
| #define SYSR_IND (1 << 5) |
| #define SYSR_SPI (1 << 0) |
| #define SYCR0_RST (0x00) |
RST bit of _SYCR0_.
SYCR0_RST resets to _WIZCHIP_ softly.
0 : Soft reset
1 : Normal operation
| #define SYCR1_IEN (1 << 7) |
IEN bit of _SYCR1_.
SYCR1_IEN is globally enable or disable the interrupt of _WIZCHIP_,
regardless of the related interrupt mask registers such as _IMR_, _SIMR_, _SLIMR_, and _Sn_IMR_.
1 : Enable
0 : Disable
| #define SYCR1_CLKSEL (1 << 0) |
System Clock select mask bit of _SYCR1_.
SYCR1_CLKSEL selects a system clock to 100MHz or 25MHz.
The masked bit values are as following.
| #define SYCR1_CLKSEL_25M 1 |
System Clock - 25MHz.
SYCR1_CLKSEL_25M selects a system clock to 25MHz.
| #define SYCR1_CLKSEL_100M 0 |
System Clock - 100MHz.
SYCR1_CLKSEL_100M selects a system clock to 100MHz.
| #define IR_WOL (1<<7) |
| #define IR_UNR6 (1<<4) |
| #define IR_IPCONF (1<<2) |
| #define IR_UNR4 (1<<1) |
| #define IR_PTERM (1<<0) |
| #define SIR_INT | ( | N | ) | (1<<N) |
N-th INT bit of @ref _SIR_.
SIR_INT(N) is set when _Sn_IR_(N) is not equal to zero.
| #define SLIR_TOUT (1<<7) |
| #define SLIR_ARP4 (1<<6) |
ARP4 bit of _SLIR_.
SLIR_ARP4 is set when the ARP-relay is received successfully after SLCR_ARP4 is performed
and the destination hardware address can be checked by _SLDHAR_.
Otherwise, SLIR_TOUT is set.
| #define SLIR_PING4 (1<<5) |
PING4 bit of _SLIR_.
SLIR_PING4 is set when the PING-relay is received successfully after SLCR_PING4 is performed
and the destination hardware address can be checked by _SLDHAR_ like as SLIR_ARP4.
Otherwise, SLIR_TOUT is set.
| #define SLIR_ARP6 (1<<4) |
ARP6 bit of _SLIR_.
SLIR_ARP6 is set when the ARP6-relay is received successfully after SLCR_ARP6 is performed
and the destination hardware address can be checked by _SLDHAR_.
Otherwise, SLIR_TOUT is set.
| #define SLIR_PING6 (1<<3) |
PING6 bit of _SLIR_.
SLIR_PING6 is set when the PING-relay is received successfully after SLCR_PING6 is performed
and the destination hardware address can be checked by _SLDHAR_ like as SLIR_ARP6.
Otherwise, SLIR_TOUT is set.
| #define SLIR_NS (1<<2) |
NS bit of _SLIR_.
SLIR_NS is set when the ICMPv6 NA is received after SLCR_NS is performed.
Its set means IPv6 address such like as _LLAR_ or _GUAR_ is conflict.
If SLIR_TOUT is set, You can use _SLDIP6R_ to _LLAR_ or _GUAR_.
| #define SLIR_RS (1<<1) |
RS bit of _SLIR_.
SLIR_RS is set when the ICMPv6 RA is received successfully after SLCR_RS is performed
and the prefix length, the prefix flag, the valid life time, the preferred life time and the prefix address of RA option message
can be checked by _PLR_, _PFR_, _VLTR_, _PLTR_ and _PAR_, respectively.
Otherwise, SLIR_TOUT is set.
| #define SLIR_RA (1<<0) |
ICMPv6 RA Received Interrupt.
SLIR_RA is set when a RA is received from a router without SLCR_RS.
Like as SLIR_RS, a RA option message can be checked by _PLR_, _PFR_, _VLTR_, _PLTR_ and _PAR_.
| #define PSR_AUTO (0x00) |
Select the source IPv6 address of the packet sent by _SLCR_ or _Sn_CR_ to AUTO.
The source IPv6 address depends on IPv6 address type of _SLDIP6R_ or _Sn_DIP6R_.
If _Sn_DIP6R_ is a link-local, the source IPv6 address is selected to _LLAR_.
Otherwise, the source IPv6 address is selected to _GUAR_.
| #define PSR_LLA (0x02) |
Select the source IP address of the packet sent by _SLCR_ or _Sn_CR_ to _LLAR_.
Regardless of the destination IPv6 address type of _SLDIP6R_ or _Sn_DIP6R_, the source IP is selected to _LLAR_.
| #define PSR_GUA (0x03) |
Select the source IP address of the packet sent by _SLCR_ or _Sn_CR_ to _GUAR_.
Regardless of the destination IPv6 address type of _SLDIP6R_, or _Sn_DIP6R_, the source IP is selected to _GUAR_.
| #define SLCR_ARP4 (1<<6) |
IPv4 ARP Command.
It sends a IPv4 ARP request message to _SLDIP4R_ without SOCKETn.
The results can be ether SLIR_TOUT or SLIR_ARP4.
If the result is SLIR_ARP4, It is success to receive the reply from _SLDIP4R_.
You can check the destination hardware address thru _SLDHAR_.
SLIR_TOUT is set when it is no reply from _SLDIP4R_
while both the time set by _SLRTR_ and the retry count set by _SLRCR_ are expired.
| #define SLCR_PING4 (1<<5) |
IPv4 PING Command.
It sends a IPv4 PING request message to _SLDIP4R_ without SOCKETn.
The results can be ether SLIR_TOUT or SLIR_PING4.
If the result is SLIR_PING4, It is success to receive the reply from _SLDIP4R_.
Also such like as SLCR_ARP4, You can check the destination hardware address thru _SLDHAR_.
SLIR_TOUT is set when it is no reply from _SLDIP4R_
while both the time set by _SLRTR_ and the retry count set by _SLRCR_ are expired.
| #define SLCR_ARP6 (1<<4) |
IPv6 ARP Command.
It sends a IPv6 ARP request message to _SLDIP6R_ without SOCKETn.
The results can be either SLIR_TOUT or SLIR_ARP6. If the result is SLIR_ARP6, It is success to receive the reply from _SLDIP6R_.
You can check the destination hardware address thru _SLDHAR_.
SLIR_TOUT is set when it is no reply from _SLDIP6R_ while both the time set by _SLRTR_ and the retry count set by _SLRCR_ are expired.
| #define SLCR_PING6 (1<<3) |
IPv6 PING Command.
It sends a IPv6 PING request message to _SLDIP6R_ without SOCKET.
The results can be either SLIR_TOUT or SLIR_PING6.
If the result is SLIR_PING6, It is success to receive the reply from _SLDIP6R_.
Also such like as SLCR_ARP6, You can check the destination hardware address thru _SLDHAR_.
SLIR_TOUT is set when it is no reply from _SLDIP6R_
while both the time set by _SLRTR_ and the retry count set by _SLRCR_ are expired.
| #define SLCR_NS (1<<2) |
IPv6 DAD(Duplicate Address Detection) NS Command.
It sends NS message for DAD to _SLDIP6R_ that is set the address to be used as as _LLAR_ or _GUAR_, without SOCKET.
The result can be ether SLIR_TOUT and SLIR_NS.
If SLIR_TOUT is set then you can use _SLDIP6R_ to _LLAR_ or _GUAR_,
else if SLIR_NS is set then you can not use _SLDIP6R_ to _LLAR_ or _GUAR_.
That means the IPv6 Address are Conflict.
| #define SLCR_RS (1<<1) |
IPv6 Auto-configuration RS Command.
It sends RS message to All-router for IPv6 Auto-configuration without SOCKET.
The result can be ether SLIR_RS or SLIR_TOUT.
If the result is SLIR_RS, You can some information of router such as a prefix length, a Prefix flag, a valid life time,
a preferred life time, and a prefix address respectively thru _PLR_, _PFR_, _VLTR_, _PLTR_, and _PAR_.
SLIR_TOUT is set when it is no reply from a IPv6 router
while both the time set by _SLRTR_ and the retry count set by _SLRCR_ are expired.
| #define SLCR_UNA (1<<0) |
IPv6 Unsolicited NA Command.
It sends the IPv6 unsolicited NA message for updating the network information such as _LLAR_, _GUAR_, and _SHAR_.
The result is none.
When _SLPSR_ = PSR_GUA, It can send the GUA unsolicited NA message.
When _SLPSR_ = Others, It can send the LLA unsolicited NA message.
| #define PHYSR_CAB (1<<7) |
CAB mask bit.
PHYSR_CAB masks the CAB bit of _PHYSR_.
The masked bit values are as following.
| #define PHYSR_CAB_OFF (1<<7) |
Ethernet Cable Off.
PHYSR_CAB_OFF indicates the cable is off the Ethernet PHY.
| #define PHYSR_CAB_ON (0<<7) |
Ethernet PHY Cable On.
PHYSR_CAB_OFF indicates the cable is on the Ethernet PHY.
| #define PHYSR_MODE (7<<3) |
Mask bits of _PHYSR_.
PHYSR_MODE masks the MODE bits of _PHYSR_.
The masked bits values are as following.
| #define PHYSR_MODE_AUTO (0<<3) |
PHY Mode - AUTO.
PHYSR_MODE_AUTO indicates the Ethernet PHY is operated as auto-negotiation mode.
| #define PHYSR_MODE_100F (4<<3) |
PHY Mode - 100F.
PHYSR_MODE_100F indicates the Ethernet PHY is operated as 100M full-duplex mode.
| #define PHYSR_MODE_100H (5<<3) |
PHY Mode - 100H.
PHYSR_MODE_100H indicates the Ethernet PHY is operated as 100M half-duplex mode.
| #define PHYSR_MODE_10F (6<<3) |
PHY Mode - 10F.
PHYSR_MODE_10F indicates the Ethernet PHY is operated as 10M full-duplex mode.
| #define PHYSR_MODE_10H (7<<3) |
PHY Mode - 10H.
PHYSR_MODE_10H indicates the Ethernet PHY is operated as 10M half-duplex mode.
| #define PHYSR_DPX (1<<2) |
DPX mask bit of _PHYSR_.
PHYSR_DPX masks the DPX bit of _PHYSR_.
The masked bit values are as following.
| #define PHYSR_DPX_HALF (1<<2) |
PHY Duplex - HALF.
PHYSR_DPX_HALF indicates the Ethernet PHY is operated as half-duplex mode.
| #define PHYSR_DPX_FULL (0<<2) |
PHY Duplex - FULL.
PHYSR_DPX_FULL indicates the Ethernet PHY is operated as full-duplex mode.
| #define PHYSR_SPD (1<<1) |
SPD mask bit of _PHYSR_.
PHYSR_SPD masks the SPD bit of _PHYSR_. The masked bit values are as following.
| #define PHYSR_SPD_10M (1<<1) |
PHY Speed - 10M.
PHYSR_SPD_10M indicates the Ethernet PHY is operated as 10Mbps speed.
| #define PHYSR_SPD_100M (0<<1) |
PHY Speed - 100M.
PHYSR_SPD_100M indicates the Ethernet PHY is operated as 100Mbps speed.
| #define PHYSR_LNK (1<<0) |
LNK mask bit of _PHYSR_.
PHYSR_LNK masks the LNK bit of _PHYSR_. The masked bit values are as following.
| #define PHYSR_LNK_UP (1<<0) |
PHY Link - Up.
PHYSR_LNK_UP indicates the link of Ethernet PHY is successfully established .
| #define PHYSR_LNK_DOWN (0<<0) |
PHY Link - Down.
PHYSR_LNK_DOWN indicates the link of Ethernet PHY is not established yet.
| #define PHYACR_READ (0x02) |
Read a value from the Ethernet PHY register specified by _PHYRAR_.
The read value can be checked by _PHYDOR_.
| #define PHYACR_WRITE (0x01) |
Write _PHYDIR_ to the Ethernet PHY register specified by _PHYRAR_.
| #define PHYDIVR_32 (0x00) |
PHY's MDC clock is the divided the system clock by 32.
| #define PHYDIVR_64 (0x01) |
PHY's MDC clock is the divided system clock by 64.
| #define PHYDIVR_128 (0xFF) |
PHY's MDC clock is the divided system clock by 128.
| #define PHYCR0_AUTO (0x00) |
PHY Operation Mode - Auto Negotiation.
PHYCR0_AUTO sets the Ethernet PHY to operate on auto-negotiation mode.
The Ethernet PHY can operate on auto-negotiation after PHYCR1_RST is performed,
and the result of PHYCR0_AUTO can be checked by PHYSR_SPD, PHYSR_DPX, and PHYSR_LNK.
| #define PHYCR0_100F (0x04) |
PHY Operation Mode - 100F.
PHYCR0_100F sets the Ethernet PHY to operate on 100F
The Ethernet PHY can operate on 100F after PHYCR1_RST is performed,
and the result of PHYCR0_100F can be checked by PHYSR_SPD, PHYSR_DPX, and PHYSR_LNK.
| #define PHYCR0_100H (0x05) |
PHY Operation Mode - 100H.
PHYCR0_100H sets the Ethernet PHY to operate on 100H
The Ethernet PHY can operate 100H after PHYCR1_RST is performed,
and the result of PHYCR0_100H can be checked by PHYSR_SPD, PHYSR_DPX, and PHYSR_LNK.
| #define PHYCR0_10F (0x06) |
PHY Operation Mode - 10F.
PHYCR0_10F sets the Ethernet PHY to operate on 10F
The Ethernet PHY can operate 10H after PHYCR1_RST is performed,
and the result of PHYCR0_10F can be checked by PHYSR_SPD, PHYSR_DPX, and PHYSR_LNK.
| #define PHYCR0_10H (0x07) |
PHY Operation Mode - 10H.
PHYCR0_10H sets the Ethernet PHY to operate on 10H
The Ethernet PHY can operate 10H after PHYCR1_RST is performed,
and the result of PHYCR0_10H can be checked by PHYSR_SPD, PHYSR_DPX, and PHYSR_LNK.
| #define PHYCR1_PWDN (1<<5) |
PHY function - Power Down.
PHYCR1_PWDN enters the Ethernet PHY in power down mode.
0 : Normal mode
1 : Power down mode
| #define PHYCR1_TE (1<<3) |
PHY function - 10Base-TE Mode.
PHYCR1_TE sets the operation of Ethernet PHY to 10base-Te.
| #define PHYCR1_RST (1<<0) |
PHY function - HW Reset.
PHYCR1_RST resets the Ethernet PHY in hardware,
and it is automatically cleared after the H/W reset and it takes 60.3ms to stabilize.
0 : Normal mode
1 : H/W Reset
| #define NETxMR_UNRB (1<<3) |
UDP Unreachable Packet Block.
NETxMR_UNRB can block sending a ICMPv or ICMPv6 unreachable message to a peer.
| #define NETxMR_PARP (1<<2) |
PING ARP Request.
NETxMR_PARP can send a ARP request before sending a ICMPv4 or ICMPv6 PING reply.
| #define NETxMR_RSTB (1<<1) |
TCP Reset Packet Block.
NETxMR_RSTB can block sending a TCP RST packet based on IPv4 or IPv6
when there is no SOCKET n opened with a listen port.
| #define NETxMR_PB (1<<0) |
PING Reply Block.
NETxMR_PB can block sending a ICMPv4 or ICMPv6 PING reply to a peer.
| #define NETMR_ANB (1<<5) |
All-node Multicating PING Reply Block.
NETMR_ANB can block sending a IPv6 PING reply to the peer ping requested to all-node multicast address.
| #define NETMR_M6B (1<<4) |
Solicited Multicasting PING Reply Block.
NETMR_M6B can block sending a IPv6 PING reply to the peer ping requested to the own solicited multicast address.
| #define NETMR_WOL (1<<2) |
Wake On LAN mode.
NETMR_WOL can receive a magic packet of WOL.
| #define NETMR_IP6B (1<<1) |
IPv6 Packet Block.
NETMR_IP6B can block receiving all IPv6 packets.
| #define NETMR_IP4B (1<<0) |
IPv4 Packet Block.
NETMR_IP4B can block receiving all IPv4 packets.
| #define NETMR2_DHAS (1<<7) |
Destination Hardware Address Select.
NETMR2_DHAS masks the DHAS bit of _NETMR2_.
The masked bit values are as following.
| #define NETMR2_DHAS_ARP (1<<7) |
Destination Hardware Address Select - ARP.
NETMR2_DHAS_ARP select the target address of ARP-replay packet to the destination hardware address.
| #define NETMR2_DHAS_ETH (0<<7) |
Destination Hardware Address Select - Ethernet Frame.
NETMR2_DHAS_ETH select the destination address of Ethernet frame to the destination hardware address.
| #define NETMR2_PPPoE (1<<0) |
PPPoE Mode.
NETMR2_PPPoE enables PPPoE mode
0 : Disable
1 : Enable
| #define ICMP6BLKR_PING6 (1<<4) |
ICMPv6 PING Block.
ICMP6BLKR_PING6 can block a ping request from a peer
| #define ICMP6BLKR_MLD (1<<3) |
ICMPv6 MLD Block.
ICMP6BLKR_MLD can block a multicast listener discovery(MLD) query.
| #define ICMP6BLKR_RA (1<<2) |
ICMPv6 RA Block.
ICMP6BLKR_RA can block a RA packet from a router
| #define ICMP6BLKR_NA (1<<1) |
ICMPv6 NA Block.
ICMP6BLKR_NA can block a Neighbor Advertisement(NA) from a peer
| #define ICMP6BLKR_NS (1<<0) |
ICMPv6 NS Block.
ICMP6BLKR_NS can block a Neighbor Solicitation(NS) from a peer
| #define Sn_MR_MULTI (1<<7) |
UDP Multicasting.
Sn_MR_MULTI enables to a multicast packet from a multicast group in UDP mode SOCKETn.
To use multicasting, _Sn_DIPR_, _Sn_DIP6R_, & _Sn_DPORTR_ should be respectively set with
the multicast group IPv4, IPv6 address & port number before Sn_CR_OPEN.
0 : Disable Multicasting
1 : Enable Multicasting
| #define Sn_MR_MF (1<<7) |
MAC Filter.
Sn_MR_MF filters other packets except broadcasting, multicasting, and packets sent to your own.
0 : Disable MAC Filtering
1 : Enable MAC Filtering
| #define Sn_MR_BRDB (1<<6) |
Broadcasting packet block.
Sn_MR_BRDB can block a broadcasting packet in MACRAW SOCKET0 or UDP mode SOCKETn.
0 : Disable Broadcast Blocking
1 : Enable Broadcast Blocking
| #define Sn_MR_FPSH (1<<6) |
Force PUSH flag.
When Sn_MR_FPSH is set, all TCP DATA packets with PSH flag set can be transmitted by Sn_CR_SEND.
When Sn_MR_FPSH is not set, the PSH flag is set only in the last DATA packet among the DATA packets transmitted by Sn_CR_SEND.
0 : No Force PSH flag
1 : Force PSH flag
| #define Sn_MR_ND (1<<5) |
No Delayed Ack.
When Sn_MR_FPSH is set, It sends the ACK packet without delay as soon as a DATA packet is received from a peer.
Otherwise, It sends the ACK packet after waiting the time set by _Sn_RTR_.
0 : Delayed ACK
1 : No Delayed ACK
| #define Sn_MR_MC (1<<5) |
IGMP version for IPv4 Multicasting.
Sn_MR_MC decides IGMP version.
0 : IGMPv2
1 : IGMPv1
| #define Sn_MR_SMB (1<<5) |
Solicited Mulitcast Block.
Sn_MR_SMB can block a received packet that have your own solicited multicast address.
0 : Unblock a solicited multicast packet
1 : Block a solicited multicast packet
| #define Sn_MR_MMB (1<<5) |
UDP4 Multicast Block.
Sn_MR_MMB can block the UDP4 multicast packet when SOCKET0 is opend with Sn_MR_MACRAW and Sn_MR_MF is set.
0 : Unblock a UDP multicast packet with IPv4 address
1 : Block a UDP multicast packet with IPv4 address
| #define Sn_MR_UNIB (1<<4) |
Unicast Block.
Sn_MR_UNIB can block a unicast packet.
0 : Unblock a UDP unicast packet
1 : Block a UDP unicast packet
| #define Sn_MR_MMB6 (1<<4) |
UDP6 Multicast Block.
Sn_MR_MMB6 can block the UDP6 multicast packet.
0 : Unblock a UDP multicast packet with IPv6 address
1 : Block a UDP multicast packet with IPv6 address
| #define Sn_MR_CLOSE (0x00) |
SOCKETn Closed.
Sn_MR_CLOSE is not opened yet.
It is the default mode when _WIZCHIP_ is reset.
| #define Sn_MR_TCP (0x01) |
IPv4 TCP mode.
Sn_MR_TCP(= Sn_MR_TCP4) sets SOCKETn to TCP4 mode.
It should be set before Sn_CR_OPEN is performed.
After Sn_CR_OPEN, SOCKETn is opend as TCP4 mode and _Sn_SR_ is changed from SOCK_CLOSED to SOCK_INIT.
| #define Sn_MR_UDP (0x02) |
IPv4 UDP mode.
Sn_MR_UDP(= Sn_MR_UDP4) sets SOCKETn to UDP4 mode.
It should be set before Sn_CR_OPEN is performed.
After Sn_CR_OPEN, SOCKETn is opend as UDP4 mode and _Sn_SR_ is changed from SOCK_CLOSED to SOCK_UDP.
| #define Sn_MR_IPRAW (0x03) |
IPv4 RAW mode.
Sn_MR_IPRAW(= Sn_MR_IPRAW4) sets SOCKETn to IPRAW4 mode.
It should be set before Sn_CR_OPEN is performed.
After Sn_CR_OPEN, SOCKETn is opend as IPRAW4 mode and _Sn_SR_ is changed from SOCK_CLOSED to SOCK_IPRAW(= SOCK_IPRAW4).
| #define Sn_MR_IPRAW4 (Sn_MR_IPRAW) |
Refer to Sn_MR_IPRAW.
| #define Sn_MR_MACRAW (0x07) |
MACRAW mode.
Sn_MR_MACRAW sets only SOCKET0 to MACRAW mode.
It should be set before Sn_CR_OPEN is performed.
After Sn_CR_OPEN, SOCKET0 is opend as MACRAW mode and _Sn_SR_ is changed from SOCK_CLOSED to SOCK_MACRAW.
| #define Sn_MR_TCP6 (0x09) |
IPv6 TCP mode.
Sn_MR_TCP6 sets SOCKETn to TCP6 mode.
It should be set before Sn_CR_OPEN is performed.
After Sn_CR_OPEN, SOCKETn is opend as TCP6 mode and _Sn_SR_ is changed from SOCK_CLOSED to SOCK_INIT.
| #define Sn_MR_UDP6 (0x0A) |
IPv6 UDP mode.
Sn_MR_UDP6 sets SOCKETn to UDP6 mode.
It should be set before Sn_CR_OPEN is performed.
After Sn_CR_OPEN, SOCKETn is opend as UDP6 mode and _Sn_SR_ is changed from SOCK_CLOSED to SOCK_UDP.
| #define Sn_MR_IPRAW6 (0x0B) |
IPv6 RAW mode.
Sn_MR_IPRAW6 sets SOCKETn to IPRAW6 mode.
It should be set before Sn_CR_OPEN is performed.
After Sn_CR_OPEN, SOCKETn is opened as IPRAW6 mode and _Sn_SR_ is changed from SOCK_CLOSED to SOCK_IPRAW6.
| #define Sn_MR_TCPD (0x0D) |
Both IPv4 & IPv6 TCP mode (TCP dual mode)
Sn_MR_TCPD sets SOCKETn to both TCP4 & TCP6 mode.
It should be set before Sn_CR_OPEN is performed.
After Sn_CR_OPEN, SOCKETn is opened as TCP Dual mode and _Sn_SR_ is changed from SOCK_CLOSED to SOCK_INIT.
The real mode of TCP dual SOCKETn is decided when the connection with a peer is established.
| #define Sn_MR_UDPD (0x0E) |
UDP Dual mode.
Sn_MR_UDPD sets SOCKETn to both UDP4 & UDP6 mode.
It should be set before Sn_CR_OPEN is performed.
After Sn_CR_OPEN, SOCKETn is opened as UDP dual mode
and _Sn_SR_ is changed from SOCK_CLOSED to SOCK_UDP.
| #define Sn_CR_OPEN (0x01) |
Initialize or Open SOCKETn.
SOCKETn is initialized and opened according to the protocol mode selected by _Sn_MR_ and with a source port set by _Sn_PORTR_.
The table shows _Sn_SR_ is changed according to _Sn_MR_.
| #define Sn_CR_LISTEN (0x02) |
Wait a connection request in TCP SERVER mode.
SOCKETn operates as a TCP SERVER and waits for a connection-request (SYN packet)
with corresponding _Sn_PORTR_ port number from any TCP CLIENT
The _Sn_SR_ is changed from SOCK_INIT to SOCK_LISTEN.
When a TCP CLIENT connection request is successfully accepted,
the _Sn_SR_ is changed from SOCK_LISTEN to SOCK_ESTABLISHED
and the Sn_IR_CON is set.
But when a TCP CLIENT connection request is failed,
Sn_IR_TIMEOUT is set and _Sn_SR_ is changed to SOCK_CLOSED.
| #define Sn_CR_CONNECT (0x04) |
Send a connection request in TCP CLIENT mode.
To establish a connection, a connect-request (SYN packet) is sent to TCP SERVER set by _Sn_DIPR_ & _Sn_DPORTR_.
If the connect-request is successful accepted by a TCP SERVER,
the _Sn_SR_ is changed to SOCK_ESTABLISHED and the Sn_IR_CON is set.
The connect-request fails in the following three cases,
and _Sn_SR_ is changed to SOCK_CLOSED.
1. Until a ARP timeout is occurred (Sn_IR_TIMEOUT = 1), a destination hardware address can not be acquired through the ARP-process.
2. Until a TCP tmeout occurred (Sn_IR_TIMEOUT = 1), a SYN/ACK packet is not received from the server
3. When a RST packet is received instead of a SYN/ACK packet
| #define Sn_CR_CONNECT6 (0x84) |
Send connection request in TCP CLIENT mode.
To establish a connection, a connect-request (SYN packet) is sent to TCP SERVER set by _Sn_DIP6R_ & _Sn_DPORTR_.
If the connect-request is successful accepted by a TCP SERVER,
the _Sn_SR_ is changed to SOCK_ESTABLISHED and the Sn_IR_CON is set.
The connect-request fails in the following three cases, and _Sn_SR_ is changed SOCK_CLOSED.
1. Until a ARP timeout is occurred (Sn_IR_TIMEOUT = 1), a destination hardware address can not be acquired through the ARP-process.
2. Until a TCP tmeout occurred (Sn_IR_TIMEOUT = 1), a SYN/ACK packet is not received from the server
3. When a RST packet is received instead of a SYN/ACK packet
| #define Sn_CR_DISCON (0x08) |
Send a disconnect request in TCP mode.
Regardless of TCP SERVER or TCP CLIENT,
Sn_CR_DISCON processes the disconnect-process (Active or Passive close).
When the disconnect-process is successful (that is, FIN/ACK packet is received successfully from/to each other),
_Sn_SR_ is changed to SOCK_CLOSED.
Otherwise, Sn_IR_TIMEOUT is set and then _Sn_SR_ is changed to SOCK_CLOSED.
| #define Sn_CR_CLOSE (0x10) |
Release or Close SOCKETn.
In TCP mode, Sn_CR_CLOSE force to close a SOCKETn without the disconnect-process.
In other SOCKETn mode, Sn_CR_CLOSE just closes a SOCKET.
| #define Sn_CR_SEND (0x20) |
Send Data.
Sn_CR_SEND send the saved data from _Sn_TX_RD_ to _Sn_TX_WR_ in the SOCKETn TX buffer
to the destination specified by _Sn_DIPR_ or _Sn_DIP6R_, and _Sn_DPORTR_.
| #define Sn_CR_SEND6 (0xA0) |
Send Data.
Sn_CR_SEND6 sends the saved data from _Sn_TX_RD_ to _Sn_TX_WR_ in the SOCKETn TX buffer
to the destination specified by _Sn_DIP6R_, and _Sn_DPORTR_.
| #define Sn_CR_SEND_KEEP (0x22) |
Send keep alive message.
Sn_CR_SEND_KEEP checks whether the connection is established or not by sending 1 byte KA(Keep Alive) packet.
If the destination can not respond to the KA packet during the time set by _Sn_RTR_ and _Sn_RCR_,
the connection is terminated, Sn_IR_TIMEOUT is set and then _Sn_SR_ is changed SOCK_CLOSED.
| #define Sn_CR_RECV (0x40) |
Receive data.
Sn_CR_RECV reads the saved from _Sn_RX_RD_ to _Sn_RX_WR_ data in SOCKETn RX buffer.
When a data is saved in the SOCKETn RX buffer,
Sn_IR_RECV is set and _Sn_RX_RSR_ is increased as many as the saved data size.
The total size of saved data is calculated by the absolute difference between _Sn_RX_WR_ and _Sn_RX_RD_,
and it can be checked thru _Sn_RX_RSR_.
After reading data, _Sn_RX_RD_ should be increased as many as the read size before Sn_CR_RECV is performed.
After Sn_CR_RECV, _Sn_RX_RSR_ is decreased as many as the read size.
If _Sn_RX_RSR_ is remained still at none-zero, Sn_IR_RECV is set again.
| #define Sn_IR_SENDOK (0x10) |
SEND OK Interrupt.
Sn_IR_SENDOK is set when it is started to be sent data by Sn_CR_SEND.
| #define Sn_IR_TIMEOUT (0x08) |
TIMEOUT Interrupt.
Sn_IR_TIMEOUT is set when a timeout occurs in ARP and ND process or TCP retransmission.
| #define Sn_IR_RECV (0x04) |
RECV Interrupt.
Sn_IR_RECV is set whenever data is received from a peer,
or if _Sn_RX_RSR_ is still at none-zero whenever Sn_CR_RECV is performed.
| #define Sn_IR_DISCON (0x02) |
DISCON Interrupt.
Sn_IR_DISCON is set when a FIN or FIN/ACK packet is received from the connected peer.
| #define Sn_IR_CON (0x01) |
CONNECT Interrupt.
Sn_IR_CON is set once the connection with a peer is established and _Sn_SR_ is changed to SOCK_ESTABLISHED.
| #define SOCK_CLOSED (0x00) |
SOCKETn Closed status.
SOCK_CLOSED indicates that SOCKETn is closed and released.
It is set when Sn_CR_DISCON , Sn_CR_CLOSE is performed, or when Sn_IR_TIMEOUT is set.
It can be changed to SOCK_CLOSED regardless of previous status.
| #define SOCK_INIT (0x13) |
TCP SOCKETn initialized status.
SOCK_INIT indicates SOCKETn is opened with TCP mode such as Sn_MR_TCP4, Sn_MR_TCP6, and Sn_MR_TCP6.
_Sn_SR_ is changed from SOCK_CLOSED to SOCK_INIT when Sn_CR_OPEN is performed in TCP mode.
In SOCK_INIT status, Sn_CR_LISTEN for operating a TCP SERVER
or Sn_CR_CONNECT / Sn_CR_CONNECT6 for operating a TCP CLIENT can be performed.
| #define SOCK_LISTEN (0x14) |
TCP SOCKETn Listen status.
SOCK_LISTEN indicates SOCKETn is operating as TCP SERVER mode
and waiting for connection-request (SYN packet) from a peer (TCP CLIENT).
_Sn_SR_ is changed to SOCK_SYNRECV when the connection-request(SYN packet) is successfully accepted
and It is changed from SOCK_SYNRECV to SOCK_ESTABLISHED
when the SYN/ACK packet is sent successfully to the peer and then the ACK packet of SYN/ACK is received successfully.
Otherwise, it is changed to SOCK_CLOSED and Sn_IR_TIMEOUT is set.
| #define SOCK_SYNSENT (0x15) |
TCP Connection Request status.
SOCK_SYNSENT indicates TCP SOCKETn sent the connect-request packet(SYN packet)
to the peer specified by _Sn_DIPR_ / _Sn_DIP6R_ and _Sn_DPORTR_.
It is temporarily shown when _Sn_SR_ is changing from SOCK_INIT to SOCK_ESTABLISHED by Sn_CR_CONNECT or Sn_CR_CONNECT6.
When the connect-accept packet (SYN/ACK packet) is received from the peer at SOCK_SYNSENT and the ACK packet of SYN/ACK is sent successfully,
_Sn_SR_ is changed to SOCK_ESTABLISHED.
Otherwise, it is changed to SOCK_CLOSED and Sn_IR_TIMEOUT is set.
| #define SOCK_SYNRECV (0x16) |
TCP Connection Accept status.
SOCK_SYNRECV indicates TCP SOCKETn is successfully received the connect-request packet (SYN packet) from a peer.
It is temporarily shown when _Sn_SR_ is changing from SOCK_LISTEN to SOCK_ESTABLISHED by the SYN packet
If SOCKETn sends the response (SYN/ACK packet) to the peer successfully and the ACK packet of SYS/ACK is received successfully,
_Sn_SR_ is changed to SOCK_ESTABLISHED.
Otherwise, _Sn_SR_ is changed to SOCK_CLOSED and Sn_IR_TIMEOUT is set.
| #define SOCK_ESTABLISHED (0x17) |
TCP SOCKETn Established status.
SOCK_ESTABLISHED indicates TCP SOCKETn is connected successfully with a peer.
when the TCP SERVER processes the SYN packet from the TCP CLIENT during SOCK_LISTEN or
when the TCP CLIENT performs successfully Sn_CR_CONNECT or Sn_CR_CONNECT6,
_Sn_SR_ is changed to SOCK_ESTABLISHED and Sn_IR_CON is set.
During SOCK_ESTABLISHED, a DATA packet can be sent to or received from the peer by Sn_CR_SEND or Sn_CR_RECV.
If the DATA/ACK packet is not received from the peer during data re-transmission, Sn_IR_TIMEOUT is set and _Sn_SR_ is changed to SOCK_CLOSED.
Otherwise, _Sn_SR_ is still at SOCK_ESTABLISHED.
| #define SOCK_FIN_WAIT (0x18) |
TCP SOCKETn Closing status.
SOCK_FIN_WAIT indicates TCP mode SOCKETn waits until the disconnect-process is completed.
It is temporarily shown in disconnect-process such as active-close.
When the disconnect-process is successfully completed or when Sn_IR_TIMEOUT is set,
_Sn_SR_ is changed to SOCK_CLOSED.
| #define SOCK_TIME_WAIT (0x1B) |
TCP SOCKETn Closing status.
SOCK_TIME_WAIT indicates TCP SOCKETn waits until the disconnect-process is completed.
It is temporarily shown in disconnect-process such as active-close.
When the disconnect-process is successfully completed or when Sn_IR_TIMEOUT is set,
_Sn_SR_ is changed to SOCK_CLOSED.
| #define SOCK_CLOSE_WAIT (0x1C) |
TCP SOCKETn Half Closing staus.
SOCK_CLOSE_WAIT indicates TCP SOCKETn receives the disconnect-request (FIN packet) from the connected peer.
It is a half-closing status, and a DATA packet can be still sent or received by Sn_CR_SEND or Sn_CR_RECV.
If you do not have any more need to send or received a DATA packet, You can perform Sn_CR_DISCON for a full-closing.
| #define SOCK_LAST_ACK (0x1D) |
TCP SOCKETn Closing status.
SOCK_LAST_ACK indicates TCP SOCKETn waits until the disconnect-process is completed.
It is temporarily shown in disconnect-process such as active-close and passive-close.
When the disconnect-process is successfully completed or when Sn_IR_TIMEOUT is set,
_Sn_SR_ is changed to SOCK_CLOSED.
| #define SOCK_UDP (0x22) |
UDP SOCKETn status.
SOCK_UDP indicates SOCKETn is opened in UDP mode such as Sn_MR_UDP4, Sn_MR_UDP6, and Sn_MR_UDPD.
_Sn_SR_ is changed from SOCK_CLOSED to SOCK_INIT when Sn_CR_OPEN is performed in UDP mode.
Unlike TCP mode, during SOCK_UDP,
a DATA packet can be sent to or received from a peer by Sn_CR_SEND / Sn_CR_SEND6 or Sn_CR_RECV without a connect-process.
Before a DATA packet is sent by Sn_CR_SEND / Sn_CR_SEND6,
the ARP is requested to the peer specified by _Sn_DIPR_ / _Sn_DIP6R_.
In ARP processing, _Sn_SR_ is stll at SOCK_UDP even if Sn_IR_TIMEOUT is set.
If you do not have any more need to send or received a DATA packet,
You can perform Sn_CR_CLOSE and _Sn_SR_ is changed to SOCK_CLOSED.
| #define SOCK_IPRAW4 (0x32) |
IPRAW4 SOCKETn mode.
SOCK_IPRAW4(= SOCK_IPRAW) SOCKETn indicates SOCKETn is opened as IPv4 RAW mode.
_Sn_SR_ is changed from SOCK_CLOSED to SOCK_IPRAW4 when Sn_CR_OPEN is performed with Sn_MR_IPRAW4.
A DATA packet can be send to or received from a peer without a connection like as SOCK_UDP.
Before a DATA packet is sent by Sn_CR_SEND,
the ARP is requested to the peer specified by _Sn_DIPR_.
In ARP processing, _Sn_SR_ is still at SOCK_IPRAW4 even if Sn_IR_TIMEOUT is set.
IPRAW4 SOCKETn can receive only the packet specified by _Sn_PNR_, and it discards the others packets.
If you do not have any more need to send or received a DATA packet,
You can perform Sn_CR_CLOSE and _Sn_SR_ is changed to SOCK_CLOSED.
| #define SOCK_IPRAW (SOCK_IPRAW4) |
Refer to SOCK_IPRAW4.
| #define SOCK_IPRAW6 (0x33) |
IPRAW6 SOCKETn mode.
SOCK_IPRAW6 SOCKETn indicates SOCKETn is opened as IPv6 RAW mode.
_Sn_SR_ is changed from SOCK_CLOSED to SOCK_IPRAW6 when Sn_CR_OPEN is performed with Sn_MR_IPRAW6.
A DATA packet can be send to or received from a peer without a connection like as SOCK_UDP.
Before a DATA packet is sent by Sn_CR_SEND6,
the ICMPv6 NS is requested to the peer specified by _Sn_DIPR_ or _Sn_DIP6R_.
In ND(Neighbor Discovery) is processing,
_Sn_SR_ is still at SOCK_IPRAW6 even if Sn_IR_TIMEOUT is set.
IPRAW6 SOCKETn can receive only the packet specified by _Sn_PNR_, and it discards the others packets.
If you do not have any more need to send or received a DATA packet,
You can perform Sn_CR_CLOSE and _Sn_SR_ is changed to SOCK_CLOSED.
| #define SOCK_MACRAW (0x42) |
MACRAW SOCKETn mode.
SOCK_MACRAW indicates SOCKET0 is opened as MACRAW mode.
_Sn_SR_ is changed from SOCK_CLOSED to SOCK_MACRAW when Sn_CR_OPEN command is ordered with Sn_MR_MACRAW.
MACRAW SOCKET0 can be sent or received a pure Ethernet frame packet to/from any peer.
| #define Sn_ESR_TCPM (1<<2) |
SOCKETn Extended Status : TCP Mode.
Sn_ESR_TCPM masks the TCPM bit of _Sn_ESR_.
The masked bit values are as following.
| #define Sn_ESR_TCPM_IPV4 (0<<2) |
TCP SOCKETn IP version - IPv4.
Sn_ESR_TCPM_IPV4 indicates TCP SOCKETn is operated on IPv4 .
| #define Sn_ESR_TCPM_IPV6 (1<<2) |
TCP SOCKETn IP version - IPv6.
Sn_ESR_TCPM_IPV6 indicates TCP SOCKETn is operated on IPv6 .
| #define Sn_ESR_TCPOP (1<<1) |
SOCKETn Extended Status : TCP Operation Mode.
Sn_ESR_TCPOP masks the TCPOP bit of _Sn_ESR_. The masked bit values are as following.
| #define Sn_ESR_TCPOP_SVR (0<<1) |
TCP SOCKETn Operation Mode - TCP SERVER
Sn_ESR_TCPOP_SVR indicates TCP mode SOCKET n is operated as TCP SERVER
| #define Sn_ESR_TCPOP_CLT (1<<1) |
TCP SOCKETn Operation Mode - TCP CLIENT
Sn_ESR_TCPOP_SVR indicates TCP mode SOCKET n is operated as TCP CLIENT
| #define Sn_ESR_IP6T (1<<0) |
SOCKETn Extended Status : Source IPv6 Address Type.
Sn_ESR_IP6T masks the IP6T bit of _Sn_ESR_.
The masked bit values are as following.
| #define Sn_ESR_IP6T_LLA (0<<0) |
Source IPv6 Address Type - LLA.
Sn_ESR_IP6T_LLA indicates the source IPv6 Address is used as _LLAR_
| #define Sn_ESR_IP6T_GUA (1<<0) |
Source IPv6 Address Type - LLA.
Sn_ESR_IP6T_GUA indicates the source IPv6 Address is used as _GUAR_
| #define Sn_MR2_DHAM (1<<1) |
Destination Hardware Address Mode.
Sn_MR2_DHAM masks the DHAM bit of _Sn_MR2_.
The masked bit values are as following.
| #define Sn_MR2_DHAM_AUTO (0<<1) |
Destination Hardware Address Mode - AUTO.
Sn_MR2_DHAM_AUTO sets the destination hardware address as the address acquired by ARP-process.
| #define Sn_MR2_DHAM_MANUAL (1<<1) |
Destination Hardware Address Mode - MANUAL.
Sn_MR2_DHAM_MANUAL sets the destination hardware address as _Sn_DHAR_.
| #define Sn_MR2_FARP (1<<0) |
Force ARP.
Sn_MR2_FARP force to perform the ARP-process for acquiring the destination hardware address, before data communication
0 : Normal
1 : Force ARP
| #define BMCR_RST (1<<15) |
Ethernet PHY S/W Reset.
0 - Normal operation
1 - Software reset
| #define BMCR_LB (1<<14) |
Ethernet PHY Loopback.
0 - Normal Operation
1 - Loopback Enable
| #define BMCR_SPD (1<<13) |
Ethernet PHY Speed.
0 - 10 Mbps
1 - 100 Mbps
| #define BMCR_ANE (1<<12) |
Ethernet PHY Auto-Negotiation.
0 - Disable
1 - Enable
| #define BMCR_PWDN (1<<11) |
Ethernet PHY Power Down Mode.
0 - Normal Operation
1 - Power Down mode
| #define BMCR_ISOL (1<<10) |
| #define BMCR_REAN (1<<9) |
| #define BMCR_DPX (1<<8) |
Ethernet PHY Duplex.
0 - Half-Duplex
1 - Full-Duplex
| #define BMCR_COLT (1<<7) |
| #define BMSR_100_T4 (1<<15) |
Ethernet PHY 100 Base-T4 capable.
BMSR_100_T4 is always 0.
| #define BMSR_100_FDX (1<<14) |
Ethernet PHY 100 Base-TX Full-Duplex capable.
BMSR_100_FDX is always 1.
| #define BMSR_100_HDX (1<<13) |
Ethernet PHY 100 Base-TX Half-Duplex capable.
BMSR_100_HDX is always 1.
| #define BMSR_10_FDX (1<<12) |
Ethernet PHY 10 Base-T Full-Duplex capable.
BMSR_10_FDX is always 1.
| #define BMSR_10_HDX (1<<11) |
Ethernet PHY 10 Base-T Half-Duplex capable.
BMSR_10_HDX is always 1.
| #define BMSR_MF_SUP (1<<6) |
Ethernet PHY Management Frame preamble suppression.
BMSR_MF_SUP is always 0.
| #define BMSR_AN_COMP (1<<5) |
Ethernet PHY Auto-Negotiation Complete.
BMSR_MF_SUP indicates the status of auto-negotiation.
0 - Auto-negotiation process is not completed
1 - Auto-negotiation process is completed
| #define BMSR_REMOTE_FAULT (1<<4) |
Ethernet PHY Remote Fault.
BMSR_REMOTE_FAULT is always 0.
| #define BMSR_AN_ABILITY (1<<3) |
Ethernet PHY Auto-Negotiation Ability.
BMSR_AN_ABILITY is always 1.
| #define BMSR_LINK_STATUS (1<<2) |
Ethernet PHY Link Status.
BMSR_LINK_STATUS indicates the status of link.
0 - Link is not established 1 - Valid link is established
| #define BMSR_JABBER_DETECT (1<<1) |
Ethernet PHY Jabber Detect.
BMSR_JABBER_DETECT indicates the status of auto-negotiation.
0 - Jabber condition is not detected
1 - Jabber condition is detected
| #define BMSR_EXT_CAPA (1<<0) |
Ethernet PHY Extended capability.
BMSR_EXT_CAPA indicates the extended register capability.
0 - Only basic registers are capable
1 - Extended registers are capable
| #define WIZCHIP_CRITICAL_ENTER | ( | ) | WIZCHIP.CRIS._e_n_t_e_r_() |
Enter a critical section.
It is provided to protect your shared code and hardware resources against interference.
| #define WIZCHIP_CRITICAL_EXIT | ( | ) | WIZCHIP.CRIS._e_x_i_t_() |
Enter a critical section.
It exits the protected code and hardware resources against interference.
| void wiz_mdio_write | ( | uint8_t | phyregaddr, |
| uint16_t | var | ||
| ) |
Write data to the PHY via MDC/MDIO interface.
Write command data to the PHY via MDC/MDIO interface.
| phyregaddr | Address of the PHY register. It should be PHYRAR_BMCR, PHYRAR_BMSR, and etc. |
| var | Data to write to the PHY register. Please refer to the bit definitions of the BMCR and BMSR register. |
Referenced by wizphy_reset(), wizphy_setphyconf(), and wizphy_setphypmode().
| uint16_t wiz_mdio_read | ( | uint8_t | phyregaddr | ) |
Read data from the PHY via MDC/MDIO interface.
Read command or status data from the PHY via MDC/MDIO interface.
| phyregaddr | Address of the PHY register. It should be PHYRAR_BMCR, PHYRAR_BMSR, and etc. |
Referenced by wizphy_getphyconf(), wizphy_getphylink(), wizphy_getphypmode(), wizphy_reset(), wizphy_setphyconf(), and wizphy_setphypmode().
1.8.17