Common register group
. More...

Macros
#define	_CIDR_ (_W6100_IO_BASE_ + (0x0000 << 8) + WIZCHIP_CREG_BLOCK)
	Chip Identification Register address [RO] [0x6100]. More...

#define	_VER_ (_W6100_IO_BASE_ + (0x0002 << 8) + WIZCHIP_CREG_BLOCK)
	Chip Version Register address [RO] [0x4661]. More...

#define	_SYSR_ (_W6100_IO_BASE_ + (0x2000 << 8) + WIZCHIP_CREG_BLOCK)
	System Status Register address [RO] [0xEU]. More...

#define	_SYCR0_ (_W6100_IO_BASE_ + (0x2004 << 8) + WIZCHIP_CREG_BLOCK)
	System Config Register 0 address [WO][0x80]. More...

#define	_SYCR1_ (WIZCHIP_OFFSET_INC(_SYCR0_,1))
	System Config Register 1 address [R=W][0x80]. More...

#define	_TCNTR_ (_W6100_IO_BASE_ + (0x2016 << 8) + WIZCHIP_CREG_BLOCK)
	Ticker Counter Register address [RO][0x0000]. More...

#define	_TCNTRCLR_ (_W6100_IO_BASE_ + (0x2020 << 8) + WIZCHIP_CREG_BLOCK)
	Ticker Counter Clear Register address [RO][0x00]. More...

#define	_IR_ (_W6100_IO_BASE_ + (0x2100 << 8) + WIZCHIP_CREG_BLOCK)
	Interrupt Register address [RO][0x00]. More...

#define	_SIR_ (_W6100_IO_BASE_ + (0x2101 << 8) + WIZCHIP_CREG_BLOCK)
	SOCKET Interrupt Register address [RO][0x00]. More...

#define	_SLIR_ (_W6100_IO_BASE_ + (0x2102 << 8) + WIZCHIP_CREG_BLOCK)
	SOCKET-less Interrupt Register address [RO][0x00]. More...

#define	_IMR_ (_W6100_IO_BASE_ + (0x2104 << 8) + WIZCHIP_CREG_BLOCK)
	Interrupt Mask Register address [R=W][0x00]. More...

#define	_IRCLR_ (_W6100_IO_BASE_ + (0x2108 << 8) + WIZCHIP_CREG_BLOCK)
	_IR_ Clear Register address [WO][0x00] More...

#define	_SIMR_ (_W6100_IO_BASE_ + (0x2114 << 8) + WIZCHIP_CREG_BLOCK)
	SOCKET Interrupt Mask Register address [R=W]][0x00]. More...

#define	_SLIMR_ (_W6100_IO_BASE_ + (0x2124 << 8) + WIZCHIP_CREG_BLOCK)
	SOCKET-less Interrupt Mask Register address [R=W][0x00]. More...

#define	_SLIRCLR_ (_W6100_IO_BASE_ + (0x2128 << 8) + WIZCHIP_CREG_BLOCK)
	SOCKET-less Interrupt Clear Register address [WO][0x00]. More...

#define	_SLPSR_ (_W6100_IO_BASE_ + (0x212C << 8) + WIZCHIP_CREG_BLOCK)
	SOCKET-less Prefer Source IPv6 Address Register address [R=W][0x00]. More...

#define	_SLCR_ (_W6100_IO_BASE_ + (0x2130 << 8) + WIZCHIP_CREG_BLOCK)
	SOCKET-less Command Register address [RW,AC][0x00]. More...

#define	_PHYSR_ (_W6100_IO_BASE_ + (0x3000 << 8) + WIZCHIP_CREG_BLOCK)
	PHY Status Register address [RO][0x00]. More...

#define	_PHYRAR_ (_W6100_IO_BASE_ + (0x3008 << 8) + WIZCHIP_CREG_BLOCK)
	PHY Internal Register Address Register address(R/W) More...

#define	_PHYDIR_ (_W6100_IO_BASE_ + (0x300C << 8) + WIZCHIP_CREG_BLOCK)
	PHY Data Input Register address [R=W][0x00]. More...

#define	_PHYDOR_ (_W6100_IO_BASE_ + (0x3010 << 8) + WIZCHIP_CREG_BLOCK)
	PHY Data Output Register address [WO][0x00]. More...

#define	_PHYACR_ (_W6100_IO_BASE_ + (0x3014 << 8) + WIZCHIP_CREG_BLOCK)
	PHY Access Register address [RW,AC][0x00]. More...

#define	_PHYDIVR_ (_W6100_IO_BASE_ + (0x3018 << 8) + WIZCHIP_CREG_BLOCK)
	PHY's MDC Clock Division Register address [R=W][0x01]. More...

#define	_PHYCR0_ (_W6100_IO_BASE_ + (0x301C << 8) + WIZCHIP_CREG_BLOCK)
	PHY Control Register address [WO][0x00]. More...

#define	_PHYCR1_ WIZCHIP_OFFSET_INC(_PHYCR0_,1)
	PHY Control Register address [R=W][0x40]. More...

#define	_NET4MR_ (_W6100_IO_BASE_ + (0x4000 << 8) + WIZCHIP_CREG_BLOCK)
	Network IPv4 Mode Register address [R=W][0x00]. More...

#define	_NET6MR_ (_W6100_IO_BASE_ + (0x4004 << 8) + WIZCHIP_CREG_BLOCK)
	Network IPv6 Mode Register address [R=W][0x00]. More...

#define	_NETMR_ (_W6100_IO_BASE_ + (0x4008 << 8) + WIZCHIP_CREG_BLOCK)
	Network Mode Register address [R=W][0x00]. More...

#define	_NETMR2_ (_W6100_IO_BASE_ + (0x4009 << 8) + WIZCHIP_CREG_BLOCK)
	Network Mode Register 2 address [R=W][0x00]. More...

#define	_PTMR_ (_W6100_IO_BASE_ + (0x4100 << 8) + WIZCHIP_CREG_BLOCK)
	PPP LCP request Timer Register address [R=W][0x28]. More...

#define	_PMNR_ (_W6100_IO_BASE_ + (0x4104 << 8) + WIZCHIP_CREG_BLOCK)
	PPP LCP Magic Number Register address [R=W][0x00]. More...

#define	_PHAR_ (_W6100_IO_BASE_ + (0x4108 << 8) + WIZCHIP_CREG_BLOCK)
	PPPoE Hardware Address Register address [R=W][0x00]. More...

#define	_PSIDR_ (_W6100_IO_BASE_ + (0x4110 << 8) + WIZCHIP_CREG_BLOCK)
	PPP Session ID Register address [R=W][0X0000]. More...

#define	_PMRUR_ (_W6100_IO_BASE_ + (0x4114 << 8) + WIZCHIP_CREG_BLOCK)
	PPP Maximum Receive Unit Register address [R=W][0xFFFF]. More...

#define	_SHAR_ (_W6100_IO_BASE_ + (0x4120 << 8) + WIZCHIP_CREG_BLOCK)
	Source Hardware Address Register address [R=W][00:00:00:00:00:00]. More...

#define	_GAR_ (_W6100_IO_BASE_ + (0x4130 << 8) + WIZCHIP_CREG_BLOCK)
	IPv4 Gateway Address Register address [R=W][0.0.0.0]. More...

#define	_GA4R_ (_GAR_)
	Refer to _GAR_. More...

#define	_SUBR_ (_W6100_IO_BASE_ + (0x4134 << 8) + WIZCHIP_CREG_BLOCK)
	IPv4 Subnet Mask Register address [R=W][0.0.0.0]. More...

#define	_SUB4R_ (_SUBR_)
	Refer to _SUBR_. More...

#define	_SIPR_ (_W6100_IO_BASE_ + (0x4138 << 8) + WIZCHIP_CREG_BLOCK)
	IPv4 Source IP Register address [R=W][0.0.0.0]. More...

#define	_SIP4R_ (_SIPR_)
	Refer to _SIPR_. More...

#define	_LLAR_ (_W6100_IO_BASE_ + (0x4140 << 8) + WIZCHIP_CREG_BLOCK)
	IPv6 LLA(Link Local Address) Register address [R=W][::]. More...

#define	_GUAR_ (_W6100_IO_BASE_ + (0x4150 << 8) + WIZCHIP_CREG_BLOCK)
	IPv6 GUA(Global Unicast Address) Register address [R=W][::]. More...

#define	_SUB6R_ (_W6100_IO_BASE_ + (0x4160 << 8) + WIZCHIP_CREG_BLOCK)
	IPv6 Subnet Mask Register address [R=W][]. More...

#define	_GA6R_ (_W6100_IO_BASE_ + (0x4170 << 8) + WIZCHIP_CREG_BLOCK)
	IPv6 Gateway Address Register address [R/W][::]. More...

#define	_SLDIP6R_ (_W6100_IO_BASE_ + (0x4180 << 8) + WIZCHIP_CREG_BLOCK)
	SOCKET-less Peer IPv6 Register address [R=W][::]. More...

#define	_SLDIPR_ (_W6100_IO_BASE_ + (0x418C << 8) + WIZCHIP_CREG_BLOCK)
	SOCKET-less Peer IPv6 Register address [R=W][0.0.0.0]. More...

#define	_SLDIP4R_ (_SLDIPR_)
	Refer to _SLDIPR_. More...

#define	_SLDHAR_ (_W6100_IO_BASE_ + (0x4190 << 8) + WIZCHIP_CREG_BLOCK)
	SOCKET-less Peer Hardware Address Register address [RO][00:00:00:00:00:00]. More...

#define	_PINGIDR_ (_W6100_IO_BASE_ + (0x4198 << 8) + WIZCHIP_CREG_BLOCK)
	SOCKET-less Ping ID Register address [R=W][0x00]. More...

#define	_PINGSEQR_ (_W6100_IO_BASE_ + (0x419C << 8) + WIZCHIP_CREG_BLOCK)
	SOCKET-less ping Sequence number Register address [R=W][0x0000]. More...

#define	_UIPR_ (_W6100_IO_BASE_ + (0x41A0 << 8) + WIZCHIP_CREG_BLOCK)
	IPv4 Unreachable Address Register address [RO][0.0.0.0]. More...

#define	_UIP4R_ (_UIPR_)
	Refer to _UPORTR_. More...

#define	_UPORTR_ (_W6100_IO_BASE_ + (0x41A4 << 8) + WIZCHIP_CREG_BLOCK)
	IPv4 Unreachable Port number Register address [RO][0x0000]. More...

#define	_UPORT4R_ (_UPORTR_)
	Refer to _UPORTR_. More...

#define	_UIP6R_ (_W6100_IO_BASE_ + (0x41B0 << 8) + WIZCHIP_CREG_BLOCK)
	IPv6 Unreachable IP Address Register address [RO][::]. More...

#define	_UPORT6R_ (_W6100_IO_BASE_ + (0x41C0 << 8) + WIZCHIP_CREG_BLOCK)
	IPv6 Unreachable Port number Register address [RO][0x0000]. More...

#define	_INTPTMR_ (_W6100_IO_BASE_ + (0x41C5 << 8) + WIZCHIP_CREG_BLOCK)
	Interrupt Pending Time Register address [R=w][0x0000]. More...

#define	_PLR_ (_W6100_IO_BASE_ + (0x41D0 << 8) + WIZCHIP_CREG_BLOCK)
	RA Prefix Length Register address [RO][0x00]. More...

#define	_PFR_ (_W6100_IO_BASE_ + (0x41D4 << 8) + WIZCHIP_CREG_BLOCK)
	RA Prefix Flag Register address [RO][0x00]. More...

#define	_VLTR_ (_W6100_IO_BASE_ + (0x41D8 << 8) + WIZCHIP_CREG_BLOCK)
	RA Valid Life Time Register address [RO][0x00000000]. More...

#define	_PLTR_ (_W6100_IO_BASE_ + (0x41DC << 8) + WIZCHIP_CREG_BLOCK)
	RA Prefered Life Time Register address [RO][0x00000000]. More...

#define	_PAR_ (_W6100_IO_BASE_ + (0x41E0 << 8) + WIZCHIP_CREG_BLOCK)
	RA Prefix Address Register address[RO][::]. More...

#define	_ICMP6BLKR_ (_W6100_IO_BASE_ + (0x41F0 << 8) + WIZCHIP_CREG_BLOCK)
	ICMPv6 Block Register address [R=W][0x00]. More...

#define	_CHPLCKR_ (_W6100_IO_BASE_ + (0x41F4 << 8) + WIZCHIP_CREG_BLOCK)
	Chip configuration Lock Register address [WO][0x00]. More...

#define	_NETLCKR_ (_W6100_IO_BASE_ + (0x41F5 << 8) + WIZCHIP_CREG_BLOCK)
	Network configuration Lock Register address [WO][0x00]. More...

#define	_PHYLCKR_ (_W6100_IO_BASE_ + (0x41F6 << 8) + WIZCHIP_CREG_BLOCK)
	PHY configuration Lock Register address [WO][0x00]. More...

#define	_RTR_ (_W6100_IO_BASE_ + (0x4200 << 8) + WIZCHIP_CREG_BLOCK)
	Retransmission Time Register address [R=W][0x07D0]. More...

#define	_RCR_ (_W6100_IO_BASE_ + (0x4204 << 8) + WIZCHIP_CREG_BLOCK)
	Retransmission Counter Register address [R=W][0x08]. More...

#define	_SLRTR_ (_W6100_IO_BASE_ + (0x4208 << 8) + WIZCHIP_CREG_BLOCK)
	SOCKET-less Retransmission Time Register address [R=W][0x07D0]. More...

#define	_SLRCR_ (_W6100_IO_BASE_ + (0x420C << 8) + WIZCHIP_CREG_BLOCK)
	SOCKET-less Retransmission Count Register address [R=W][0x00]. More...

#define	_SLHOPR_ (_W6100_IO_BASE_ + (0x420F << 8) + WIZCHIP_CREG_BLOCK)
	SOCKET-less Hop Limit Register address [R=W][0x80]. More...

#define	PHYRAR_BMCR (0x00)
	Basic Mode Control Register of Ethernet PHY [RW][0x3100]. More...

#define	PHYRAR_BMSR (0x01)
	Basic Mode Status Register of Ethernet PHY [RO][0x7809]. More...

Detailed Description

Common register group
.

It set the general configuration such as interrupt, network information, ICMP, and etc.

See also

_WIZCHIP_ Information	: _CIDR_, _VER_
_WIZCHIP_ Mode	: _SYSR_, _SYCR0_, _SYCR1_, _CHPLCKR_, _NETLCKR_, _PHYLCKR_
Network Mode	: _NET4MR_, _NET6MR_, _NETMR_, _NETMR2_
Network Information	: _GAR_, _SUBR_, _SHAR_, _SIPR_, _GA6R_, _LLAR_, _GUAR_, _SUB6R_
Interrupt	: _IR_, _IRCLR_, _IMR_, _SIR_, _SIMR_, _SLIR_, _SLIMR_, _SLIRCLR_, _INTPTMR_
Data retransmission	: _RTR_, _RCR_, _SLRTR_, _SLRCR_, _SLHOPR_
PPPoE	: _PHAR_, _PSIDR_, _PMRUR_, _PTMR_, _PMNR_
SOCKET-less command	: _SLCR_, _SLIR_, _SLDIPR_, _SLDIP4R_, _SLDIP6R_, _SLDHAR_, _PINGIDR_, _PINGSEQR_
ICMP v4 & v6	: _UIPR_, _UPORTR_, _UIP6R_, _UPORT6R_, _ICMP6BLKR_
IPv6 Auto-configuration	: _PLR_, _PFR_, _VLTR_, _PAR_
PHY Configuration	: _PHYSR_, _PHYCR0_, _PHYCR1_, _PHYRAR_, _PHYDIR_, _PHYDOR_, _PHYACR_, _PHYDIVR_

Macro Definition Documentation

◆ _CIDR_

#define _CIDR_ (_W6100_IO_BASE_ + (0x0000 << 8) + WIZCHIP_CREG_BLOCK)

Chip Identification Register address [RO] [0x6100].

See also: getCIDR()

Definition at line 222 of file w6100.h.

◆ _VER_

#define _VER_ (_W6100_IO_BASE_ + (0x0002 << 8) + WIZCHIP_CREG_BLOCK)

Chip Version Register address [RO] [0x4661].

See also: getVER()

Definition at line 228 of file w6100.h.

◆ _SYSR_

#define _SYSR_ (_W6100_IO_BASE_ + (0x2000 << 8) + WIZCHIP_CREG_BLOCK)

System Status Register address [RO] [0xEU].

_SYSR_ shows the information such as CHIP, NET, PHY Locking and Host I/F

7	6	5	4 ~ 2	1	0
CHPL	NETL	PHYL	Reserved	IND	SPI

SYSR_CHPL
SYSR_NETL
SYSR_PHYL
SYSR_IND : HOST use Parallel BUS Interface(Indirect Bus Mode)
SYSR_SPI : HOST use SPI Interface

See also: _CHPLCKR_, _NETLCKR_, _PHYLCKR_,; getSYSR(), setCHPLCKR(), getCHPLCKR(), CHIPLOCK(), CHIPUNLOCK(), setNETLCKR(), getNETLCKR(), NETLOCK(), NETUNLOCK()
setPHYLCKR(), getPHYLCKR(), PHYLOCK(), PHYUNLOCK()

Definition at line 247 of file w6100.h.

◆ _SYCR0_

#define _SYCR0_ (_W6100_IO_BASE_ + (0x2004 << 8) + WIZCHIP_CREG_BLOCK)

System Config Register 0 address [WO][0x80].

_SYCR0_ softly reset to _WIZCHIP_.

7	6 ~ 0
RST	Reserved

SYCR0_RST : Software Reset.

Note: It can be accessed only when SYSR_CHPL = 1.

See also: _CHPLCKR_, _SYSR_, SYSR_CHPL; setSYCR0(), setCHPLCKR(), getCHPLCKR(), CHIPLOCK(), CHIPUNLOCK(), getSYSR()

Definition at line 262 of file w6100.h.

◆ _SYCR1_

#define _SYCR1_ (WIZCHIP_OFFSET_INC(_SYCR0_,1))

System Config Register 1 address [R=W][0x80].

_SYCR1_ controls the global interrupt enable, and selects the system clock.

7	6 ~ 1	0
IEN	Reserved	CLKSEL

Note: SYCR1_CLKSEL bit can be accessed only when SYSR_CHPL = 1.

See also: _CHPLCKR_, _SYSR_, SYSR_CHPL; getSYCR1(), setSYCR1(), setCHPLCKR(), getCHPLCKR(), CHIPLOCK(), CHIPUNLOCK(), getSYSR()

Definition at line 278 of file w6100.h.

◆ _TCNTR_

#define _TCNTR_ (_W6100_IO_BASE_ + (0x2016 << 8) + WIZCHIP_CREG_BLOCK)

Ticker Counter Register address [RO][0x0000].

_TCNTR_ increase by 1 every 100us after _WIZCHIP_ reset.

See also: _TCNTRCLR_; getTCNTR(), setTCNTRCLR()

Definition at line 286 of file w6100.h.

◆ _TCNTRCLR_

#define _TCNTRCLR_ (_W6100_IO_BASE_ + (0x2020 << 8) + WIZCHIP_CREG_BLOCK)

Ticker Counter Clear Register address [RO][0x00].

_TCNTRCLR_ clear _TCNTR_.

See also: setTCNTRCLR(), getTCNTR()

Definition at line 293 of file w6100.h.

◆ _IR_

#define _IR_ (_W6100_IO_BASE_ + (0x2100 << 8) + WIZCHIP_CREG_BLOCK)

Interrupt Register address [RO][0x00].

_IR_ indicates the interrupt status. If _IR_ is not equal to x00 INTn PIN is asserted to low until it is x00.

7	6 ~ 5	4	3	2	1	0
WOL	Reserved	UNR6	Reserved	IPCONF	UNR4	PTERM

IR_WOL : Wake On LAN
IR_UNR6 : Destination Port Unreachable for IPv6
IR_IPCONF : _SIPR_ is Conflict
IR_UNR4 : Destination Port Unreachable for IPv4
IR_PTERM : PPPoE Terminated

See also: _IMR_, _IRCLR_, SYCR1_IEN, _CHIPLCKR_, _SYSR_, SYSR_CHPL; getIR(), setIRCLR(), getSYCR1(), setSYCR1(), getCHPLCKR(), setCHPLCKR(), CHIPLOCK(), CHIPUNLOCK(), getSYSR()

Definition at line 313 of file w6100.h.

◆ _SIR_

#define _SIR_ (_W6100_IO_BASE_ + (0x2101 << 8) + WIZCHIP_CREG_BLOCK)

SOCKET Interrupt Register address [RO][0x00].

_SIR_ indicates whether a socket interrupt is occurred or not.
Each bit of _SIR_ be still until _Sn_IR_ is cleared by _Sn_IRCLR_

See also: _SIMR_, _Sn_IR_, _Sn_IRCLR_, _Sn_IMR_, SYCR1_IEN , _CHIPLCKR_, _SYSR_, SYSR_CHPL; getSIR(), getSn_IR(), setSn_IRCLR(), getSIMR(), setSIMR(), getSn_IMR(), setSn_IMR(), getSYCR1(), setSYCR1(),
getSYCR1(), setSYCR1(), getCHPLCKR(), setCHPLCKR(), CHIPLOCK(), CHIPUNLOCK(), getSYSR()

Definition at line 323 of file w6100.h.

◆ _SLIR_

#define _SLIR_ (_W6100_IO_BASE_ + (0x2102 << 8) + WIZCHIP_CREG_BLOCK)

SOCKET-less Interrupt Register address [RO][0x00].

_SLIR_ indicates the completion of _SLCR_ or timeout.

7	6	5	4	3	2	1	0
TOUT	ARP4	PING4	ARP6	PING6	NS	RS	RA

SLIR_TOUT : The timeout occurrence after _SLCR_ is performed
SLIR_ARP4 : The completion of SLCR_ARP4
SLIR_PING4 : The completion of SLCR_PING4
SLIR_ARP6 : The completion f SLCR_ARP6
SLIR_PING6 : The completion of SLCR_PING6
SLIR_NS : The completion of SLCR_NS
SLIR_RS : The completion of SLIR_RS
SLIR_RA : The reception from Router Advertisement

See also: _SLIRCLR_, _SLIMR_, SYCR1_IEN, _CHPLCKR_, _SYSR_, SYSR_CHPL; getSLIR(), setSLIRCLR(), getSLIR(), getSLIMR(), setSLIMR(),
getSYCR1(), setSYCR1(), getCHPLCKR(), setCHPLCKR(), CHIPLOCK(), CHIPUNLOCK(), getSYSR()

Definition at line 345 of file w6100.h.

◆ _IMR_

#define _IMR_ (_W6100_IO_BASE_ + (0x2104 << 8) + WIZCHIP_CREG_BLOCK)

Interrupt Mask Register address [R=W][0x00].

_IMR_ is used to mask interrupts of _IR_.
When a bit of _IMR_ and the corresponding bit of _IR_ is set, an interrupt will be issued.

See also: _IR_, SYCR1_IEN, _CHPLCKR_, _SYSR_, SYSR_CHPL; getIMR(), setIMR(), getIR(), setIRCLR(),
getSYCR1(), setSYCR1(), getCHPLCKR(), setCHPLCKR(), CHIPLOCK(), CHIPUNLOCK(), getSYSR()

Definition at line 355 of file w6100.h.

◆ _IRCLR_

#define _IRCLR_ (_W6100_IO_BASE_ + (0x2108 << 8) + WIZCHIP_CREG_BLOCK)

_IR_ Clear Register address [WO][0x00]

_IRCLR_ clears _IR_

See also: _IR_, _IMR_, SYCR1_IEN, _CHPLCKR_, _SYSR_, SYSR_CHPL; setIRCLR(), getIR(), getIMR(), getSYCR1(), setSYCR1(), getCHPLCKR(), setCHPLCKR(), CHIPLOCK(), CHIPUNLOCK(), getSYSR()

Definition at line 363 of file w6100.h.

◆ _SIMR_

#define _SIMR_ (_W6100_IO_BASE_ + (0x2114 << 8) + WIZCHIP_CREG_BLOCK)

SOCKET Interrupt Mask Register address [R=W]][0x00].

_SIMR_ is used to mask interrupts of _SIR_.
When a bit of _SIMR_ and the corresponding bit of _SIR_ is set, an interrupt will be issued.
when _Sn_IR_ is not 0, The N-th bit of _SIR_ is set. Otherwise, this bit is automatically clear.

Definition at line 374 of file w6100.h.

◆ _SLIMR_

#define _SLIMR_ (_W6100_IO_BASE_ + (0x2124 << 8) + WIZCHIP_CREG_BLOCK)

SOCKET-less Interrupt Mask Register address [R=W][0x00].

_SLIMR_ is used to mask interrupts of _SLIR_
When a bit of _SLIMR_ and the corresponding bit of _SLIR_ is set, an interrupt will be issued.

See also: _SLIR_, _SLIRCLR_, SYCR1_IEN, _CHPLCKR_, _SYSR_, SYSR_CHPL; getSLIMR(), setSLIMR(), getSLIR(), setSLIRCLR(),
getSYCR1(), setSYCR1(), getCHPLCKR(), setCHPLCKR(), CHIPLOCK(), CHIPUNLOCK(), getSYSR()

Definition at line 384 of file w6100.h.

◆ _SLIRCLR_

#define _SLIRCLR_ (_W6100_IO_BASE_ + (0x2128 << 8) + WIZCHIP_CREG_BLOCK)

SOCKET-less Interrupt Clear Register address [WO][0x00].

_SLIRCLR_ clears _SLIR_

See also: _SLIR_, _SLIRCLR_, _SLIMR_, SYCR1_IEN, _CHPLCKR_, _SYSR_, SYSR_CHPL; getSLIR(), setSLIRCLR(), getSLIMR(), setSLIMR(),
getSYCR1(), setSYCR1(), getCHPLCKR(), setCHPLCKR(), CHIPLOCK(), CHIPUNLOCK(), getSYSR()

Definition at line 393 of file w6100.h.

◆ _SLPSR_

#define _SLPSR_ (_W6100_IO_BASE_ + (0x212C << 8) + WIZCHIP_CREG_BLOCK)

SOCKET-less Prefer Source IPv6 Address Register address [R=W][0x00].

_SLPSR_ select the Source IPv6 Address to transmit a packet by _SLCR_.

PSR_AUTO
PSR_LLA
PSR_GUA
See also
_SLCR_, _Sn_PSR_

getSLPSR(), setSLPSR(), getSLCR(), setSLCR(), getSn_PSR(), setSn_PSR()

Definition at line 404 of file w6100.h.

◆ _SLCR_

#define _SLCR_ (_W6100_IO_BASE_ + (0x2130 << 8) + WIZCHIP_CREG_BLOCK)

SOCKET-less Command Register address [RW,AC][0x00].

_SLCR_ can be request a message such like as ARP, PING, and ICMPv6 without SOCKET.

7	6	5	4	3	2	1	0
Reserved	ARP4	PING4	ARP6	PING6	NS	RS	UNA

Definition at line 425 of file w6100.h.

◆ _PHYSR_

#define _PHYSR_ (_W6100_IO_BASE_ + (0x3000 << 8) + WIZCHIP_CREG_BLOCK)

PHY Status Register address [RO][0x00].

_PHYSR_ shows the operation mode of PHY, the link status and etc.

See also: _PHYCR0_, _PHYLCKR_, _SYSR_, SYSR_PHYL; getPHYSR(), setPHYCR0(), setPHYLCKR(), getPHYLCKR(), PHYLOCK(), PHYUNLOCK(), getSYSR()

Definition at line 439 of file w6100.h.

◆ _PHYRAR_

#define _PHYRAR_ (_W6100_IO_BASE_ + (0x3008 << 8) + WIZCHIP_CREG_BLOCK)

PHY Internal Register Address Register address(R/W)

_PHYRAR_ specifies the address of register in the Ethernet PHY.

PHYRAR_BMCR
PHYRAR_BMSR
See also
_PHYACR_, _PHYDOR_, _PHYDIR_, _PHYDIVR_

getPHYACR(), setPHYACR(), getPHYDOR(), setPHYDIR(), getPHYDIVR(), setPHYDIVR()

Definition at line 449 of file w6100.h.

◆ _PHYDIR_

#define _PHYDIR_ (_W6100_IO_BASE_ + (0x300C << 8) + WIZCHIP_CREG_BLOCK)

PHY Data Input Register address [R=W][0x00].

_PHYDIR_ specifies the value to write to the register in PHY

See also: _PHYRAR_, _PHYACR_, _PHYDOR_, _PHYDIVR_; setPHYDIR(), getPHYRAR(), setPHYRAR(), getPHYACR(), setPHYACR(), getPHYDOR(), setPHYDIR(), getPHYDIVR(), setPHYDIVR()

Definition at line 457 of file w6100.h.

◆ _PHYDOR_

#define _PHYDOR_ (_W6100_IO_BASE_ + (0x3010 << 8) + WIZCHIP_CREG_BLOCK)

PHY Data Output Register address [WO][0x00].

_PHYDOR_ read the value from the register in PHY

See also: _PHYRAR_, _PHYACR_, _PHYDIR_, _PHYDIVR_; getPHYDOR(), getPHYRAR(), setPHYRAR(), getPHYACR(), setPHYACR(), setPHYDIR(), getPHYDIVR(), setPHYDIVR()

Definition at line 465 of file w6100.h.

◆ _PHYACR_

#define _PHYACR_ (_W6100_IO_BASE_ + (0x3014 << 8) + WIZCHIP_CREG_BLOCK)

PHY Access Register address [RW,AC][0x00].

_PHYACR_ write(read) to(from) the value of register in the Ethernet PHY

PHYACR_READ
PHYACR_WRITE
See also
_PHYRAR_, _PHYDOR_, _PHYDIR_, _PHYDIVR_

getPHYACR(), setPHYACR(), getPHYDOR(), getPHYRAR(), setPHYRAR(), setPHYDIR(), getPHYDIVR(), setPHYDIVR()

Definition at line 475 of file w6100.h.

◆ _PHYDIVR_

#define _PHYDIVR_ (_W6100_IO_BASE_ + (0x3018 << 8) + WIZCHIP_CREG_BLOCK)

PHY's MDC Clock Division Register address [R=W][0x01].

_PHYDIVR_ divides the system clock for the MDC clock of Ethernet PHY'

PHYDIVR_32
PHYDIVR_64
PHYDIVR_128
See also
_PHYRAR_, _PHYACR_, _PHYDOR_, _PHYDIR_, _PHYDIVR_

getPHYDIVR(), setPHYDIVR(), getPHYRAR(), setPHYRAR(), getPHYACR(), setPHYACR(), getPHYDOR(), setPHYDIR()

Definition at line 486 of file w6100.h.

◆ _PHYCR0_

#define _PHYCR0_ (_W6100_IO_BASE_ + (0x301C << 8) + WIZCHIP_CREG_BLOCK)

PHY Control Register address [WO][0x00].

_PHYCR0_ controls the operation mode of PHY. The result will be checked by _PHYSR_ after PHY HW reset by PHYCR1_RST.

Note: It can be only accessed when SYSR_PHYL is unlock.

See also: _SYSR_, _PHYCR1_; setPHYCR0(), getSYSR(), getPHYCR1(), setPHYCR1()

Definition at line 502 of file w6100.h.

◆ _PHYCR1_

#define _PHYCR1_ WIZCHIP_OFFSET_INC(_PHYCR0_,1)

PHY Control Register address [R=W][0x40].

_PHYCR1_ controls the Ethernet PHY function such as HW reset, Power down and etc.

7	6	5	4	3	2 ~ 1	0
Reserved	Always 1	PWDN	Reseved	TE	Reserved	RST

Note: It can be only accessed when SYSR_PHYL is unlock.

See also: _SYSR_, _PHYCR0_; getPHYCR1(), setPHYCR1(), setPHYCR0(), getSYSR()

Definition at line 519 of file w6100.h.

◆ _NET4MR_

#define _NET4MR_ (_W6100_IO_BASE_ + (0x4000 << 8) + WIZCHIP_CREG_BLOCK)

Network IPv4 Mode Register address [R=W][0x00].

_NET4MR_ can block the transmission such like as unreachable message, TCP reset, and ping relay.
It can ARP request before ping relpy.

7 ~ 4	3	2	1	0
Reserved	UNRB	PARP	RSTB	PB

NETxMR_UNRB
NETxMR_PARP
NETxMR_RSTB
NETxMR_PB
See also
_NET6MR_

getNET4MR(), setNET4MR(), getNET6MR(), setNET6MR()

Definition at line 537 of file w6100.h.

◆ _NET6MR_

#define _NET6MR_ (_W6100_IO_BASE_ + (0x4004 << 8) + WIZCHIP_CREG_BLOCK)

Network IPv6 Mode Register address [R=W][0x00].

_NET6MR_ can block the transmission such like as unreachable message, TCP reset, and ping relay.
It can ARP request before ping reply.

7 ~ 4	3	2	1	0
Reserved	UNRB	PARP	RSTB	PB

NETxMR_UNRB
NETxMR_PARP
NETxMR_RSTB
NETxMR_PB
See also
_NET4MR_

getNET6MR(), setNET6MR(), getNET4MR(), setNET4MR()

Definition at line 555 of file w6100.h.

◆ _NETMR_

#define _NETMR_ (_W6100_IO_BASE_ + (0x4008 << 8) + WIZCHIP_CREG_BLOCK)

Network Mode Register address [R=W][0x00].

_NETMR_ set WOL(Wake On Lan) mode.
It also can block a packet such as
IPv6 PING request from an all-node broadcasting,
IPv6 PING request from a solicited mulitcasting address,
IPv4 packets,
and IPv6 packets.

7 ~ 6	5	4	3	2	1	0
Reserved	ANB	M6B	Always 0	WOL	IP6B	IP4B

NETMR_ANB
NETMR_M6B
NETMR_WOL
NETMR_IP6B
NETMR_IP4B
See also
getNETMR(), setNETMR()

Definition at line 578 of file w6100.h.

◆ _NETMR2_

#define _NETMR2_ (_W6100_IO_BASE_ + (0x4009 << 8) + WIZCHIP_CREG_BLOCK)

Network Mode Register 2 address [R=W][0x00].

_NETMR2_ set PPPoE mode.
It also can select the destination hardware address to either Ethernet frame MAC or target MAC in the ARP-reply message

7	6 ~ 1	0
DHAS	6 ~ 1	PPPoE

NETMR2_DHAS : NETMR2_DHAS_ARP, NETMR2_DHAS_ETH
NETMR2_PPPoE
See also
getNETMR2(), setNETMR2()

Definition at line 592 of file w6100.h.

◆ _PTMR_

#define _PTMR_ (_W6100_IO_BASE_ + (0x4100 << 8) + WIZCHIP_CREG_BLOCK)

PPP LCP request Timer Register address [R=W][0x28].

_PTMR_ sets the time for sending LCP echo request.
The unit of time is 25ms.

See also: _PMNR_, _PHAR_, _PSIDR_, _PMRUR_, NETMR2_PPPoE; getPTMR(), setPTMR(), getPMNR(), setPMNR(), getPHAR(), setPHAR(), getPSIDR(), setPSIDR(), getPMRUR(), setPMRUR(), getNETMR2(), setNETMR2()

Definition at line 601 of file w6100.h.

◆ _PMNR_

#define _PMNR_ (_W6100_IO_BASE_ + (0x4104 << 8) + WIZCHIP_CREG_BLOCK)

PPP LCP Magic Number Register address [R=W][0x00].

_PMNR_ sets the 4bytes magic number to be used in LCP negotiation.

See also: _PTMR_, _PHAR_, _PSIDR_, _PMRUR_, NETMR2_PPPoE; getPMNR(), setPMNR(), getPTMR(), setPTMR(), getPHAR(), setPHAR(), getPSIDR(), setPSIDR(), getPMRUR(), setPMRUR(), getNETMR2(), setNETMR2()

Definition at line 609 of file w6100.h.

◆ _PHAR_

#define _PHAR_ (_W6100_IO_BASE_ + (0x4108 << 8) + WIZCHIP_CREG_BLOCK)

PPPoE Hardware Address Register address [R=W][0x00].

_PHAR_ sets the PPPoE server hardware address that is acquired during PPPoE connection process.

See also: _PTMR_, _PMNR_, _PSIDR_, _PMRUR_, NETMR2_PPPoE; getPHAR(), setPHAR(), getPTMR(), setPTMR(), getPMNR(), setPMNR(), getPSIDR(), setPSIDR(), getPMRUR(), setPMRUR(), getNETMR2(), setNETMR2()

Definition at line 617 of file w6100.h.

◆ _PSIDR_

#define _PSIDR_ (_W6100_IO_BASE_ + (0x4110 << 8) + WIZCHIP_CREG_BLOCK)

PPP Session ID Register address [R=W][0X0000].

_PSIDR_ sets the PPPoE sever session ID acquired during PPPoE connection process.

See also: _PTMR_, _PMNR_, _PHAR_, _PMRUR_, NETMR2_PPPoE; getPSIDR(), setPSIDR(), getPTMR(), setPTMR(), getPMNR(), setPMNR(), getPHAR(), setPHAR(), getPMRUR(), setPMRUR(), getNETMR2(), setNETMR2()

Definition at line 625 of file w6100.h.

◆ _PMRUR_

#define _PMRUR_ (_W6100_IO_BASE_ + (0x4114 << 8) + WIZCHIP_CREG_BLOCK)

PPP Maximum Receive Unit Register address [R=W][0xFFFF].

_PMRUR_ sets the maximum receive unit of PPPoE.

See also: _PTMR_, _PMNR_, _PHAR_, _PSIDR_, NETMR2_PPPoE; getPMRUR(), setPMRUR(), getPTMR(), setPTMR(), getPMNR(), setPMNR(), getPHAR(), setPHAR(), getPSIDR(), setPSIDR(), getNETMR2(), setNETMR2()

Definition at line 633 of file w6100.h.

◆ _SHAR_

#define _SHAR_ (_W6100_IO_BASE_ + (0x4120 << 8) + WIZCHIP_CREG_BLOCK)

Source Hardware Address Register address [R=W][00:00:00:00:00:00].

_SHAR_ sets the source hardware address.

Note: It can be accessed only when SYSR_NETL is unlock.

See also: SYSR_NETL, _NETLCKR_; getSHAR(), setSHAR(), getSYSR(), setNETLCKR(), getNETLCKR(), NETLOCK(), NETUNLOCK()

Definition at line 642 of file w6100.h.

◆ _GAR_

#define _GAR_ (_W6100_IO_BASE_ + (0x4130 << 8) + WIZCHIP_CREG_BLOCK)

IPv4 Gateway Address Register address [R=W][0.0.0.0].

_GAR_ sets the default gateway IPv4 address.

Note: It can be accessed only when SYSR_NETL is unlock.

See also: SYSR_NETL, _NETLCKR_, _GA6R_; getGAR(), setGAR(), getSYSR(), setNETLCKR(), getNETLCKR(), NETLOCK(), NETUNLOCK(), getGA6R(), setGA6R()

Definition at line 651 of file w6100.h.

◆ _GA4R_

#define _GA4R_ (_GAR_)

Refer to _GAR_.

Definition at line 652 of file w6100.h.

◆ _SUBR_

#define _SUBR_ (_W6100_IO_BASE_ + (0x4134 << 8) + WIZCHIP_CREG_BLOCK)

IPv4 Subnet Mask Register address [R=W][0.0.0.0].

_SUBR_ sets the default subnet mask address of IPv4.

Note: It can be accessed only when SYSR_NETL is unlock.

See also: SYSR_NETL, _NETLCKR_, _SUB6R_; getSUBR(), setSUBR(), getSYSR(), setNETLCKR(), getNETLCKR(), NETLOCK(), NETUNLOCK(), getSUB6R(), setSUB6R()

Definition at line 660 of file w6100.h.

◆ _SUB4R_

#define _SUB4R_ (_SUBR_)

Refer to _SUBR_.

Definition at line 661 of file w6100.h.

◆ _SIPR_

#define _SIPR_ (_W6100_IO_BASE_ + (0x4138 << 8) + WIZCHIP_CREG_BLOCK)

IPv4 Source IP Register address [R=W][0.0.0.0].

_SIPR_ sets the source IPv4 address.

Note: It can be accessed only when SYSR_NETL is unlock.

See also: SYSR_NETL, _NETLCKR_, _LLAR_, _GUAR_; getSIPR(), setSIPR(), getSYSR(), setNETLCKR(), getNETLCKR(), NETLOCK(), NETUNLOCK(), getLLAR(), setLLAR(), getGUAR(),setGUAR()

Definition at line 670 of file w6100.h.

◆ _SIP4R_

#define _SIP4R_ (_SIPR_)

Refer to _SIPR_.

Definition at line 671 of file w6100.h.

◆ _LLAR_

#define _LLAR_ (_W6100_IO_BASE_ + (0x4140 << 8) + WIZCHIP_CREG_BLOCK)

IPv6 LLA(Link Local Address) Register address [R=W][::].

_LLAR_ sets the LLA address of IPv6.

Note: It can be accessed only when SYSR_NETL is unlock.

See also: SYSR_NETL, _NETLCKR_, _GUAR_, _SIPR_; getLLAR(), setLLAR(), getSYSR(), setNETLCKR(), getNETLCKR(), NETLOCK(), NETUNLOCK(), getGUAR(),setGUAR(), getSIPR(), setSIPR()

Definition at line 680 of file w6100.h.

◆ _GUAR_

#define _GUAR_ (_W6100_IO_BASE_ + (0x4150 << 8) + WIZCHIP_CREG_BLOCK)

IPv6 GUA(Global Unicast Address) Register address [R=W][::].

_GUAR_ sets the GUA address of IPv6.

Note: It can be accessed only when SYSR_NETL is unlock.

See also: SYSR_NETL, _NETLCKR_, _LLAR_, _SIPR_; getGUAR(), setGUAR(), getSYSR(), setNETLCKR(), getNETLCKR(), NETLOCK(), NETUNLOCK(), getLLAR(),setLLAR(), getSIPR(), setSIPR()

Definition at line 689 of file w6100.h.

◆ _SUB6R_

#define _SUB6R_ (_W6100_IO_BASE_ + (0x4160 << 8) + WIZCHIP_CREG_BLOCK)

IPv6 Subnet Mask Register address [R=W][].

_SUB6R_ sets the default subnet mask address of IPv6.

Note: It can be accessed only when SYSR_NETL is unlock.

See also: SYSR_NETL, _NETLCKR_, _SUBR_; getSUB6R(), setSUB6R(), getSYSR(), setNETLCKR(), getNETLCKR(), NETLOCK(), NETUNLOCK(), getSUBR(), setSUBR()

Definition at line 698 of file w6100.h.

◆ _GA6R_

#define _GA6R_ (_W6100_IO_BASE_ + (0x4170 << 8) + WIZCHIP_CREG_BLOCK)

IPv6 Gateway Address Register address [R/W][::].

_GA6R_ sets the default gateway IPv6 address.

See also: _GAR_; getGA6R(), setGA6R(), getGAR(), setGAR()

Definition at line 706 of file w6100.h.

◆ _SLDIP6R_

#define _SLDIP6R_ (_W6100_IO_BASE_ + (0x4180 << 8) + WIZCHIP_CREG_BLOCK)

SOCKET-less Peer IPv6 Register address [R=W][::].

_SLDIP6R_ sets the destination IP address of _SLCR_.

Definition at line 715 of file w6100.h.

◆ _SLDIPR_

#define _SLDIPR_ (_W6100_IO_BASE_ + (0x418C << 8) + WIZCHIP_CREG_BLOCK)

SOCKET-less Peer IPv6 Register address [R=W][0.0.0.0].

_SLDIPR_(= _SLDIP4R_) sets the destination IPv4 address of _SLCR_.

Definition at line 724 of file w6100.h.

◆ _SLDIP4R_

#define _SLDIP4R_ (_SLDIPR_)

Refer to _SLDIPR_.

Definition at line 725 of file w6100.h.

◆ _SLDHAR_

#define _SLDHAR_ (_W6100_IO_BASE_ + (0x4190 << 8) + WIZCHIP_CREG_BLOCK)

SOCKET-less Peer Hardware Address Register address [RO][00:00:00:00:00:00].

_SLDHAR_ gets the destination hardware address acquired by of SLCR_ARP4, SLCR_ARP6, SLCR_PING4, and SLCR_PING6.

See also: _SLDIP4R_, _SLDIP6R_, _SLCR_, _SLIR_, _SLIRCLR_, _SLIMR_; getSLDHAR(), getSLDIP4R(), setSLDIP4R(), getSLDIP6R(), setSLDIP6R(), getSLCR(), setSLCR(),
getSLIR(), setSLIRCLR(), getSLIMR(), setSLIMR()

Definition at line 735 of file w6100.h.

◆ _PINGIDR_

#define _PINGIDR_ (_W6100_IO_BASE_ + (0x4198 << 8) + WIZCHIP_CREG_BLOCK)

SOCKET-less Ping ID Register address [R=W][0x00].

_PINGIDR_ sets the PING-request ID to be sent by SLCR_PING4 or SLCR_PING6.

Definition at line 744 of file w6100.h.

◆ _PINGSEQR_

#define _PINGSEQR_ (_W6100_IO_BASE_ + (0x419C << 8) + WIZCHIP_CREG_BLOCK)

SOCKET-less ping Sequence number Register address [R=W][0x0000].

_PINGIDR_ sets the PING-request sequence number to be sent by SLCR_PING4 or SLCR_PING6.

Definition at line 753 of file w6100.h.

◆ _UIPR_

#define _UIPR_ (_W6100_IO_BASE_ + (0x41A0 << 8) + WIZCHIP_CREG_BLOCK)

IPv4 Unreachable Address Register address [RO][0.0.0.0].

_UIPR_ is set when a unreachable ICMPv4 message is received.

See also: _UPORTR_, _UIP6R_, _UPORT6R_; getUIPR(), setUIPR(), getUPORTR(), setUPORTR(), getUIPR6(), setUIPR6(), getUPORT6R(), setUPORT6R()

Definition at line 761 of file w6100.h.

◆ _UIP4R_

#define _UIP4R_ (_UIPR_)

Refer to _UPORTR_.

Definition at line 762 of file w6100.h.

◆ _UPORTR_

#define _UPORTR_ (_W6100_IO_BASE_ + (0x41A4 << 8) + WIZCHIP_CREG_BLOCK)

IPv4 Unreachable Port number Register address [RO][0x0000].

_UPORTR_ is set when a unreachable ICMPv4 message is received.

See also: _UIPR_, _UIP6R_, _UPORT6R_; getUPORTR(), setUPORTR(), getUIPR(), setUIPR(), getUIPR6(), setUIPR6(), getUPORT6R(), setUPORT6R()

Definition at line 770 of file w6100.h.

◆ _UPORT4R_

#define _UPORT4R_ (_UPORTR_)

Refer to _UPORTR_.

Definition at line 771 of file w6100.h.

◆ _UIP6R_

#define _UIP6R_ (_W6100_IO_BASE_ + (0x41B0 << 8) + WIZCHIP_CREG_BLOCK)

IPv6 Unreachable IP Address Register address [RO][::].

_UIP6R_ is set when a unreachable ICMPv6 message is received.

See also: _UIPR_, _UPORTR_, _UIP6R_, _UPORT6R_; getUIPR6(), setUIPR6(), getUIPR(), setUIPR(), getUPORTR(), setUPORTR(), getUPORT6R(), setUPORT6R()

Definition at line 778 of file w6100.h.

◆ _UPORT6R_

#define _UPORT6R_ (_W6100_IO_BASE_ + (0x41C0 << 8) + WIZCHIP_CREG_BLOCK)

IPv6 Unreachable Port number Register address [RO][0x0000].

_UIP6R_ is set when a unreachable ICMPv6 message is received.

See also: _UIPR_, _UPORTR_, _UIP6R_, _UPORT6R_; getUIPR6(), setUIPR6(), getUIPR(), setUIPR(), getUPORTR(), setUPORTR(), getUPORT6R(), setUPORT6R()

Definition at line 786 of file w6100.h.

◆ _INTPTMR_

#define _INTPTMR_ (_W6100_IO_BASE_ + (0x41C5 << 8) + WIZCHIP_CREG_BLOCK)

Interrupt Pending Time Register address [R=w][0x0000].

_INTPTMR_ pends the next interrupt issued by the INTn pin of _WIZCHIP_.
It is decreased 1 every 4 SYS_CLK.
If it is zero and some interrupt is still remained, the INTn pin is issued.

See also: _IR_, _IRCLR_, _IMR_, _SIR_, _Sn_IRCLR_, _SIMR_, _SLIR_, _SLIRCLR_, _SLIMR_, SYCR_IEN; getINTPTMR(), setINTPTMR(), getIR(), setIRCLR(), getIMR(), setIMR(), getSIR(), setSn_IRCLR(), getSIMR(), setSIMR(),
getSLIR(), setSLIRCLR(), getSLIMR(), setSLIMR(), getSYCR1(), setSYCR1()

Definition at line 797 of file w6100.h.

◆ _PLR_

#define _PLR_ (_W6100_IO_BASE_ + (0x41D0 << 8) + WIZCHIP_CREG_BLOCK)

RA Prefix Length Register address [RO][0x00].

_PLR_ is set when RA packet is received from a router.

See also: SLIR_RA, _SLIRCLR_, _PFR_, _VLTR_, _PLTR_, _PAR_; getPLR(), getSLIR(), setSLIRCLR(), getPFR(), getVLTR(), getPLTR(), getPAR()

Definition at line 805 of file w6100.h.

◆ _PFR_

#define _PFR_ (_W6100_IO_BASE_ + (0x41D4 << 8) + WIZCHIP_CREG_BLOCK)

RA Prefix Flag Register address [RO][0x00].

_PFR_ is set when RA packet is received from a router.

See also: SLIR_RA, _SLIRCLR_, _PLR_, _VLTR_, _PLTR_, _PAR_; getPFR(), getSLIR(), setSLIRCLR(), getPLR(), getVLTR(), getPLTR(), getPAR()

Definition at line 813 of file w6100.h.

◆ _VLTR_

#define _VLTR_ (_W6100_IO_BASE_ + (0x41D8 << 8) + WIZCHIP_CREG_BLOCK)

RA Valid Life Time Register address [RO][0x00000000].

_VLTR_ is set when RA packet is received from a router.

See also: SLIR_RA, _SLIRCLR_, _PLR_, _PFR_, _PLTR_, _PAR_; getVLTR(), getSLIR(), setSLIRCLR(), getPLR(), getPFR(), getPLTR(), getPAR()

Definition at line 821 of file w6100.h.

◆ _PLTR_

#define _PLTR_ (_W6100_IO_BASE_ + (0x41DC << 8) + WIZCHIP_CREG_BLOCK)

RA Prefered Life Time Register address [RO][0x00000000].

_PLTR_ is set when RA packet is received from a router.

See also: SLIR_RA, _SLIRCLR_, _PLR_, _PFR_, _PLTR_, _PAR_; getPLTR(), getSLIR(), setSLIRCLR(), getPLR(), getPFR(), getVLTR(), getPAR()

Definition at line 829 of file w6100.h.

◆ _PAR_

#define _PAR_ (_W6100_IO_BASE_ + (0x41E0 << 8) + WIZCHIP_CREG_BLOCK)

RA Prefix Address Register address[RO][::].

_PAR_ is set when RA packet is received from a router.

See also: SLIR_RA, _SLIRCLR_, _PLR_, _PFR_, _VLTR_, _PLTR_, _PAR_; getPAR(), getPLTR(), getSLIR(), setSLIRCLR(), getPLR(), getPFR(), getVLTR()

Definition at line 837 of file w6100.h.

◆ _ICMP6BLKR_

#define _ICMP6BLKR_ (_W6100_IO_BASE_ + (0x41F0 << 8) + WIZCHIP_CREG_BLOCK)

ICMPv6 Block Register address [R=W][0x00].

_ICMP6BLKR_ can block ICMPv6 message such like as PING, MLD, RA, NS and NA.
In this blocked case, Sn_MR_IPRAW6 SOCKET can receive it.

7 ~ 5	4	3	2	1	0
7 ~ 5	PING6	MLD	RA	NA	NS

Note: The blocked message can be accepted by SOCKETn opened with Sn_MR_IPRAW6.

See also: NETxMR_PB; getICMP6BLKR(), setICMP6BLKR(), getNET6MR(), setNET6MR()

Definition at line 857 of file w6100.h.

◆ _CHPLCKR_

#define _CHPLCKR_ (_W6100_IO_BASE_ + (0x41F4 << 8) + WIZCHIP_CREG_BLOCK)

Chip configuration Lock Register address [WO][0x00].

_CHPLCKR_ can lock or unlock to access _SYCR0_ and _SYCR1_.
The lock state can be checked from SYSR_CHPL.

See also: _SYCR0_, _SYCR1_, _SYSR_, SYSR_CHPL; getCHPLCKR(), setCHPLCKR(), CHIPLOCK(), CHIPUNLOCK(), getSYSR()

Definition at line 866 of file w6100.h.

◆ _NETLCKR_

#define _NETLCKR_ (_W6100_IO_BASE_ + (0x41F5 << 8) + WIZCHIP_CREG_BLOCK)

Network configuration Lock Register address [WO][0x00].

_NETLCKR_ can lock or unlock to access the network information register such as _SIPR_, _LLAR_, and etc.
The lock state can be checked from @ SYSR_NETL.

See also: _SHAR_, _SIPR_, _SUBR_, _GAR_, _LLAR_, _GUAR_, _SUB6R_, _SYSR_, SYSR_NETL; getNETLCKR(), setNETLCKR(), NETLOCK(), NETUNLOCK(), getSHAR(), setSHAR(), getSIPR(), getSIPR(), getSUBR(), setSUBR(),
getGAR(), setGAR(), getLLAR(), setLLAR(), getGUAR(), setGUAR(), getSUB6R(), setSUB6R(), getSYSR()

Definition at line 876 of file w6100.h.

◆ _PHYLCKR_

#define _PHYLCKR_ (_W6100_IO_BASE_ + (0x41F6 << 8) + WIZCHIP_CREG_BLOCK)

PHY configuration Lock Register address [WO][0x00].

_PHYLCKR_ can lock or unlock to access _PHYCR0_ and _PHYCR1_.
The lock state can be checked from SYSR_PHYL.

See also: _PHYCR0_, _PHYCR1_, _SYSR_, SYSR_PHYL.; getPHYLCKR(), setPHYLCKR(), PHYLOCK(), PHYUNLOCK(), setPHYCR0(), getPHYCR1(), setPHYCR1(), getSYSR()

Definition at line 885 of file w6100.h.

◆ _RTR_

#define _RTR_ (_W6100_IO_BASE_ + (0x4200 << 8) + WIZCHIP_CREG_BLOCK)

Retransmission Time Register address [R=W][0x07D0].

_RTR_ sets the default timeout value of _Sn_RTR_.
When _Sn_RTR_ is 0, _Sn_RTR_ is reset to _RTR_ after Sn_CR_OPEN.

See also: _Sn_RTR_, _RCR_, _Sn_RCR_, _Sn_CR_, Sn_CR_OPEN, _Sn_IR_, _Sn_IRCLR_, Sn_IR_TIMEOUT; getRTR(), setRTR(), getSn_RTR(), setSn_RTR(), getRCR(), setRCR(), getSn_RCR(), setSn_RCR(),
getSn_CR(), getSn_CR(), getSn_IR(), setSn_IRCLR()

Definition at line 895 of file w6100.h.

◆ _RCR_

#define _RCR_ (_W6100_IO_BASE_ + (0x4204 << 8) + WIZCHIP_CREG_BLOCK)

Retransmission Counter Register address [R=W][0x08].

_RCR_ sets the default retransmission count of _Sn_RCR_.
When _Sn_RCR_ is 0, _Sn_RCR_ is initialized as _Sn_RTR_ after Sn_CR_OPEN.

See also: _Sn_RCR_, _RTR_, _Sn_RTR_, _Sn_CR_, Sn_CR_OPEN, _Sn_IR_, _Sn_IRCLR_, Sn_IR_TIMEOUT; getRCR(), setRCR(), getSn_RCR(), setSn_RCR(), getRTR(), setRTR(), getSn_RTR(), setSn_RTR(),
getSn_CR(), getSn_CR(), getSn_IR(), setSn_IRCLR()

Definition at line 905 of file w6100.h.

◆ _SLRTR_

#define _SLRTR_ (_W6100_IO_BASE_ + (0x4208 << 8) + WIZCHIP_CREG_BLOCK)

SOCKET-less Retransmission Time Register address [R=W][0x07D0].

_SLRTR_ sets the timeout value of packet to be retransmitted by _SLCR_.

See also: _SLRCR_, _SLIR_, _SLIRCLR_, SLIR_TOUT; getSLRTR(), setSLRTR(), getSLRCR(), setSLRCR(), getSLIR(), setSLIRCLR()

Definition at line 913 of file w6100.h.

◆ _SLRCR_

#define _SLRCR_ (_W6100_IO_BASE_ + (0x420C << 8) + WIZCHIP_CREG_BLOCK)

SOCKET-less Retransmission Count Register address [R=W][0x00].

_SLRCR_ sets the retry counter of packet to be retransmitted by _SLCR_.

See also: _SLRTR_, _SLIR_, _SLIRCLR_, SLIR_TOUT; getSLRCR(), setSLRCR(), getSLRTR(), setSLRTR(), setSLIRCLR(), getSLIR(), setSLIRCLR(),

Definition at line 921 of file w6100.h.

◆ _SLHOPR_

#define _SLHOPR_ (_W6100_IO_BASE_ + (0x420F << 8) + WIZCHIP_CREG_BLOCK)

SOCKET-less Hop Limit Register address [R=W][0x80].

_SLHOPR_ sets the hop limit value of packet to be transmitted by _SLCR_.

See also: _SLCR_; getSLHOPR(), setSLHOPR(), getSLCR(), setSLCR()

Definition at line 929 of file w6100.h.

◆ PHYRAR_BMCR

#define PHYRAR_BMCR (0x00)

Basic Mode Control Register of Ethernet PHY [RW][0x3100].

PHYRAR_BMCR can be controlled by MDC/MDIO controller of _WIZCHIP_.
Each bit of PHYRAR_BMCR is defined as the following.

15	14	13	12	11	10	9	8	7	6 ~ 0
RST	LB	SPD	ANE	PWDN	ISOL	RAN	DPX	COLT	Reserved

Note: Its some bits have the same function as _PHYCR0_ and _PHYCR1_.
It can control the Ethernet PHY with software, while _PHYCR0_
and _PHYCR1_ can control the Ethernet PHY with hardware.

See also: PHYRAR_BMSR, _PHYRAR_, _PHYDIR_, _PHYDOR_, _PHYACR_, _PHYCR0_, _PHYCR1_; getPHYRAR(), setPHYRAR(), wiz_mdio_read(), wiz_mdio_write()

Definition at line 3104 of file w6100.h.

◆ PHYRAR_BMSR

#define PHYRAR_BMSR (0x01)

Basic Mode Status Register of Ethernet PHY [RO][0x7809].

PHYRAR_BMSR gets the status of Ethernet PHY through MDC/MDIO controller of _WIZCHIP_.
Each bit of PHYRAR_BMSR is defined as the following.

15	14	13	12	11	10~7	6	5	4	3	2	1	0
100_T4	100_FDX	100_HDX	10_FDX	10_HDX	Reserved	MF_SUP	ANG_COMP	REMOTE_FAULT	ANG_ABILITY	LINK_STATUS	JABBER_DETECT	EXT_CAPA

BMSR_100_T4 : Not supported. Always 0
BMSR_100_FDX
BMSR_100_HDX
BMSR_10_FDX
BMSR_10_HDX
BMSR_MF_SUP : Not supported. Always 0.
BMSR_AN_COMP
BMSR_REMOTE_FAULT : Not supported. Always 0.
BMSR_AN_ABILITY
BMSR_LINK_STATUS
BMSR_JABBER_DETECT
BMSR_EXT_CAPA : Always 1. If you need a extended register information, send e-mail to suppo.nosp@m.rt@w.nosp@m.iznet.nosp@m..io

Note: Its some bits have the same function as _PHYSR_.

See also: PHYRAR_BMCR, _PHYRAR_, _PHYDIR_, _PHYDOR_, _PHYACR_, _PHYCR0_, _PHYCR1_; getPHYRAR(), setPHYRAR(), wiz_mdio_read(), wiz_mdio_write()

Definition at line 3135 of file w6100.h.

Macros